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LM2512ASN

更新时间: 2024-11-28 12:06:03
品牌 Logo 应用领域
德州仪器 - TI /
页数 文件大小 规格书
28页 1092K
描述
LM2512A Mobile Pixel Link (MPL-1), 24 Bit RGB Display Interface Serializer with Optional Dithering and Look Up Table

LM2512ASN 技术参数

是否无铅: 不含铅是否Rohs认证: 符合
生命周期:Obsolete零件包装代码:QFN
包装说明:HVQCCN,针数:40
Reach Compliance Code:compliant风险等级:5.62
接口集成电路类型:INTERFACE CIRCUITJESD-30 代码:S-XQCC-N40
JESD-609代码:e3长度:6 mm
湿度敏感等级:3功能数量:1
端子数量:40最高工作温度:85 °C
最低工作温度:-30 °C封装主体材料:UNSPECIFIED
封装代码:HVQCCN封装形状:SQUARE
封装形式:CHIP CARRIER, HEAT SINK/SLUG, VERY THIN PROFILE峰值回流温度(摄氏度):260
认证状态:Not Qualified座面最大高度:0.4 mm
最大供电电压:2 V最小供电电压:1.6 V
标称供电电压:1.8 V表面贴装:YES
温度等级:OTHER端子面层:TIN
端子形式:NO LEAD端子节距:0.5 mm
端子位置:QUAD处于峰值回流温度下的最长时间:40
宽度:6 mmBase Number Matches:1

LM2512ASN 数据手册

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LM2512A  
www.ti.com  
SNLS269B AUGUST 2007REVISED MAY 2013  
LM2512A Mobile Pixel Link (MPL-1), 24-Bit RGB Display Interface Serializer with Optional  
Dithering and Look Up Table  
Check for Samples: LM2512A  
1
FEATURES  
DESCRIPTION  
The LM2512A is a MPL Serializer (SER) that  
performs a 24-bit to 18-bit Dither operation and  
serialization of the video signals to Mobile Pixel link  
(MPL) levels on only 3 or 4 active signals. An optional  
Look Up Table (Three X 256 X 8 bit RAM) is also  
provided for independent color correction. 18-bit  
Bufferless or partial buffer displays from QVGA (320  
x 240) up to VGA (640 x 480) pixels can utilize a 24-  
bit video source.  
2
24-bit RGB Interface Support up to 640 x 480  
VGA Format  
Optional 24 to 18-bit Dithering  
Optional Look Up Table for Independent Color  
Correction  
MPL-1 Physical Layer  
SPI Interface for Look Up Table Control and  
Loading  
The interconnect is reduced from 28 signals to only 3  
or 4 active signals with the LM2512A and companion  
deserializer easing flex interconnect design, size  
constraints and cost.  
Low Power Consumption & Powerdown State  
Level Translation Between Host and Display  
Optional Auto Power Down on STOP PCLK  
Frame Sequence Bits Auto Resync upon Data  
or Clock Error  
The LM2512A SER resides by the application,  
graphics or baseband processor and translates the  
wide parallel video bus from LVCMOS levels to serial  
Mobile Pixel Link levels for transmission over a flex  
cable (or coax) and PCB traces to the DES located  
near or in the display module.  
1.6V to 2.0V Core / Analog Supply Voltage  
1.6V to 3.0V I/O Supply Voltage Range  
SYSTEM BENEFITS  
When in Power_Down, the SER is put to sleep and  
draws less than 10μA. The link can also be powered  
down by stopping the PCLK (DES dependant) or by  
the PD* input pins.  
Dithered Data Reduction  
Independent RGB Color Correction  
24-bit Color Input  
The LM2512A provides enhanced AC performance  
over the LM2512. It implements the physical layer of  
the MPL-1 and uses a single-ended current-mode  
transmission.  
Small Interface, Low Power and Low EMI  
Intrinsic Level Translation  
Typical 3 MD Lane Application Diagram - Bridge Chip  
LM2512A Serializer  
MPL-1 Deserializer  
MD0  
MD1  
MC  
D
Apps  
Processor  
---  
Graphics  
Processor  
---  
R[7:0]  
G[7:0]  
B[7:0]  
VS  
HS  
DE  
R[5:0]  
G[5:0]  
B[5:0]  
VS  
HS  
DE  
i
t
h
e
r
P
2
S
RGB Display  
VGA  
PCLK  
PCLK  
Baseband  
Processor  
at 18-Bit Color Depth  
MD2  
S
P
I
Three  
256 X  
8
SPI_CSX  
SPI_SCL  
SPI_SDA  
PD*  
LUT  
PLL  
PD*  
PD  
[Supply, Configuration pins,  
and bypass caps. and grounding not shown]  
OUT*  
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
All trademarks are the property of their respective owners.  
2
PRODUCTION DATA information is current as of publication date.  
Products conform to specifications per the terms of the Texas  
Instruments standard warranty. Production processing does not  
necessarily include testing of all parameters.  
Copyright © 2007–2013, Texas Instruments Incorporated  

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