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LM2502SQX PDF预览

LM2502SQX

更新时间: 2024-11-14 13:09:19
品牌 Logo 应用领域
美国国家半导体 - NSC /
页数 文件大小 规格书
27页 1084K
描述
IC LINE TRANSCEIVER, PQCC40, 5 X 5 MM, 0.80 MM HEIGHT, 0.40 MM PITCH, LEAD FREE, LLP-40, Line Driver or Receiver

LM2502SQX 技术参数

是否Rohs认证: 符合生命周期:Transferred
包装说明:HVQCCN, LCC40,.2SQ,16Reach Compliance Code:compliant
ECCN代码:EAR99HTS代码:8542.39.00.01
风险等级:5.45差分输出:NO
驱动器位数:1输入特性:SCHMITT TRIGGER
接口集成电路类型:LINE TRANSCEIVER接口标准:GENERAL PURPOSE
JESD-30 代码:S-PQCC-N40JESD-609代码:e3
长度:5 mm湿度敏感等级:3
功能数量:1端子数量:40
最高工作温度:85 °C最低工作温度:-30 °C
封装主体材料:PLASTIC/EPOXY封装代码:HVQCCN
封装等效代码:LCC40,.2SQ,16封装形状:SQUARE
封装形式:CHIP CARRIER, HEAT SINK/SLUG, VERY THIN PROFILE峰值回流温度(摄氏度):260
电源:1.8/3,3 V认证状态:Not Qualified
最大接收延迟:接收器位数:1
座面最大高度:0.8 mm子类别:Line Driver or Receivers
最大压摆率:25 mA最大供电电压:3.3 V
最小供电电压:2.9 V标称供电电压:3 V
表面贴装:YES温度等级:OTHER
端子面层:Matte Tin (Sn)端子形式:NO LEAD
端子节距:0.4 mm端子位置:QUAD
处于峰值回流温度下的最长时间:40宽度:5 mm
Base Number Matches:1

LM2502SQX 数据手册

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August 2005  
LM2502  
Mobile Pixel Link (MPL) Display Interface Serializer and  
Deserializer  
General Description  
Features  
>
n
300 Mbps Dual Link Raw Throughput  
The LM2502 device is a dual link display interface SERDES  
that adapts existing CPU / video busses to a low power  
current-mode serial MPL link. The chipset may also be used  
for a RGB565 application with glue logic. The interconnect is  
reduced from 22 signals to only 3 active signals with the  
LM2502 chipset easing flex interconnect design, size and  
cost.  
n MPL Physical Layer (MPL-0)  
n Pin selectable Master / Slave mode  
n Frequency Reference Transport  
n Complete LVCMOS / MPL Translation  
n Interface Modes:  
— 16-bit CPU, i80 or m68 style  
— RGB565 with glue logic  
n −30˚C to 85˚C Operating Range  
n Link power down mode reduces IDDZ 10 µA  
n Dual Display Support (CS1* & CS2*)  
n Via-less MPL interconnect feature  
n 3.0V Supply Voltage (VDD and VDDA  
n Interfaces to 1.7V to 3.3V Logic (VDDIO  
The Master Serializer (SER) resides beside an application  
processor or baseband processor and translates a parallel  
bus from LVCMOS levels to serial MPL levels for transmis-  
sion over a flex cable and PCB traces to the Slave Deseri-  
alizer (DES) located near the display module.  
<
Dual display support is provided for a primary and sub  
display through the use of two ChipSelect signals. A Mode  
pin selects either a i80 or m68 style interface.  
)
)
The Power_Down (PD*) input controls the power state of the  
MPL interface. When PD* is asserted, the MD1/0 and MC  
signals are powered down to save current.  
System Benefits  
n Small Interface  
n Low Power  
n Low EMI  
n Frequency Reference Transport  
n Intrinsic Level Translation  
The LM2502 implements the physical layer of the MPL Stan-  
dard (MPL-0). The LM2502 is offered in NOPB (Lead-free)  
UFBGA and LLP packages.  
Typical Application Diagram  
20093301  
Ordering Information  
NSID  
Package Type  
Package ID  
49 Lead UFBGA style, 4.0 X 4.0 X 1.0 mm, 0.5 mm pitch  
1000 std reel, LM2502SMX 4500 reel  
LM2502SM  
LM2502SQ  
SLH49A  
SQF40A  
40 Lead LLP style, 5.0 X 5.0 X 0.8 mm, 0.4 mm pitch  
1000 std reel, LM2502SQX 4500 reel  
© 2005 National Semiconductor Corporation  
DS200933  
www.national.com  

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