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LM2502

更新时间： 2024-09-18 02:58:23
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德州仪器 - TI /
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32页 1347K
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Mobile Pixel Link Display Interface Serializer and Deserializer

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LM2502 数据手册

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LM2502  
www.ti.com  
SNLS176L –JANUARY 2004–REVISED MAY 2013  
Mobile Pixel Link (MPL) Display Interface Serializer and Deserializer  
Check for Samples: LM2502  
1
FEATURES  
DESCRIPTION  
The LM2502 device is a dual link display interface  
SERDES that adapts existing CPU / video busses to  
a low power current-mode serial MPL link. The  
chipset may also be used for a RGB565 application  
with glue logic. The interconnect is reduced from 22  
signals to only 3 active signals with the LM2502  
chipset easing flex interconnect design, size and cost.  
2
•
•
•
•
•
•
>300 Mbps Dual Link Raw Throughput  
MPL Physical Layer (MPL-0)  
Pin Selectable Master / Slave Mode  
Frequency Reference Transport  
Complete LVCMOS / MPL Translation  
Interface Modes:  
The Master Serializer (SER) resides beside an  
application processor or baseband processor and  
translates a parallel bus from LVCMOS levels to  
serial MPL levels for transmission over a flex cable  
and PCB traces to the Slave Deserializer (DES)  
located near the display module.  
–
–
16-bit CPU, i80 or m68 Style  
RGB565 with Glue Logic  
•
•
•
•
•
•
−30°C to 85°C Operating Range  
Link Power Down Mode Reduces IDDZ < 10 µA  
Dual Display Support (CS1* & CS2*)  
Via-less MPL Interconnect Feature  
Dual display support is provided for a primary and  
sub display through the use of two ChipSelect  
signals. A Mode pin selects either a i80 or m68 style  
interface.  
3.0V Supply Voltage (VDD and VDDA  
)
Interfaces to 1.7V to 3.3V Logic (VDDIO  
)
The Power_Down (PD*) input controls the power  
state of the MPL interface. When PD* is asserted, the  
MD1/0 and MC signals are powered down to save  
current.  
SYSTEM BENEFITS  
•
•
•
•
•
Small Interface  
Low Power  
The LM2502 implements the physical layer of the  
MPL Standard (MPL-0). The LM2502 is offered in  
NOPB (Lead-free) NFBGA and WQFN packages.  
Low EMI  
Frequency Reference Transport  
Intrinsic Level Translation  
Typical Application Diagram  
LM2502 MPL Master  
LM2502 MPL Slave  
CLK (optional)  
INTR  
R/W*(WR*)  
E (RD*)  
A/D  
D[15:0]  
R/W*(WR*)  
R/W*  
MC  
E (RD*)  
A/D  
D[15:0]  
BBP  
or  
APP  
Processor  
MD0  
MD1  
CS2*  
CS1*  
CS2*  
CS1*  
PD*  
CLK  
Mode  
PD*  
Primary  
Display  
(A)  
Sub  
Display  
(B)  
CLKDIS*  
PLL_Con  
[2:0]  
M/S*  
M/S* = H  
PLL_CON[2:0],  
Mode are application  
dependent  
PLL_Con[2:0]  
Mode  
GND  
M/S*  
GND  
M/S* = L  
PLL_CON[2:0], Mode, CLKDIS* are application  
dependent, PD* = GPIO  
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
All trademarks are the property of their respective owners.  
2
PRODUCTION DATA information is current as of publication date.  
Products conform to specifications per the terms of the Texas  
Instruments standard warranty. Production processing does not  
necessarily include testing of all parameters.  
Copyright © 2004–2013, Texas Instruments Incorporated  
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