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LM2501SL PDF预览

LM2501SL

更新时间: 2024-09-16 22:51:55
品牌 Logo 应用领域
美国国家半导体 - NSC /
页数 文件大小 规格书
14页 300K
描述
Mobile Pixel Link (MPL) Camera Interface Serializer and Deserializer

LM2501SL 数据手册

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ADVANCE INFORMATION  
June 2004  
LM2501  
Mobile Pixel Link (MPL) Camera Interface Serializer and  
Deserializer  
General Description  
Features  
n 160 Mbps Raw Throughput  
The LM2501 device is a Serializer/Deserializer that adapts  
existing video busses to Mobile Pixel Link (MPL). MPL is  
intended to replace wide LVCMOS video interfaces inside  
portable electronics equipment benefiting their cost, size,  
EMI and power consumption.  
n MPL-0 Meets MPL Physical Layer Specification  
n Configurable as a Serializer or Deserializer  
n Complete LVCMOS to MPL Translation  
n Serializes 8-bit Camera Interface  
— 8-bit color data  
— plus VSYNC and HSYNC bits  
n Link power down mode reduces quiescent power under  
10 µA (actual TBD)  
By using the LM2501 SERDES chipset, the interconnect is  
reduced from 12 active signals to only 3 active signals  
providing a 75% reduction. This eases interconect and flex  
design, size and cost.  
Contained in a 24 lead Ultra Thin CSP Package, the Serial-  
izer resides beside the video source (camera) and translates  
the parallel bus from LVCMOS levels to serial MPL levels for  
transmission over a flex cable to the Deserializer located by  
the respective destination Video Input Port.  
n 1.7V–3.1V and 2.9-3.1V Supply Voltage  
n Interfaces to 1.8V–3.0V Logic  
n Offered in a small 24L UCSP Package  
— 3.5 mm X 4.5 mm  
— 0.6 mm Max Height  
An extra clock transport is provided to deliver a clock signal  
to the target. For example, from the main board to the flip  
board where the camera module is located. Transmission of  
the clock also benefits from MPL’s low power transmission  
and low EMI.  
System Benefits  
n Reduced Wire Interface  
n Low Power  
n Low EMI  
n Extra Clock Transport  
n Intrinsic Level Translation  
The Power_Down (PD*) input controls the power state of the  
MPL interface. When PD* is asserted, the MD, MC and WC  
signals are powered down to save current and reduce power  
dissipation.  
Typical Application Diagram  
20091601  
Ordering Information  
NSID  
Package Type  
24-Lead Ultra Thin CSP 3.5 X 4.5 X 0.6 mm  
Package ID  
LM2501SL  
SLE24A  
I2C® is a registered trademark of Phillips Corporation.  
© 2004 National Semiconductor Corporation  
DS200916  
www.national.com  

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