National Semiconductor
Application Note 2129
Vijay Choudhary
Boot Capacitor Regulation
in LM25007 Constant-On-
Time (COT) Converter
March 14, 2011
see Figure 1. This voltage is usually referred to as prebias.
Since, at startup, there is no current in the inductor (L), the
prebias voltage at the output appears at the switch node. If
this prebias voltage is high such that the boot capacitor volt-
age (VBST=VCC-VSW) is lower than the threshold voltage
(VTH) of high side gate, the high side switch fails to turn 'on'
and the converter fails to startup see Figure 2 . This condition
persists until prebias is removed. A prebias is often caused
by some leakage path in downstream circuits, e.g., a logic
circuit or FPGA with a pin pulled high, or leftover charge from
a previous power down.
The Issue
LM25000 series of constant-on-time (COT) integrated regu-
lators provide a simple, cost-effective way of implementing a
step down buck regulator with nearly fixed frequency. Non-
synchronous operation reduces switching frequency at very
light load resulting in higher efficiency than a comparable
fixed frequency converter. The non-synchronous operation,
however, causes two problems related to boot capacitor reg-
ulation under certain operating conditions.
Bootstrap capacitor (CBST) may have insufficient voltage dur-
ing startup if a voltage is present at the output of the converter
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FIGURE 1. LM25007 Application with Prebiased Output
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FIGURE 2. Startup with Prebiased Output
A similar situation may occur under light load or no load con-
ditions see Figure 3. At light load/no load, the inductor current
is discontinuous causing the diode (D1) to turn off for a rela-
tively long off time. During this time the bootstrap capacitor
(CBST) may discharge to a level below the top side FET gate
drive threshold (VTH), which is normally around 5V. Under
these conditions the top side FET fails to turn on and the out-
put voltage is no longer regulated. Since there is no current
in the inductor, this output voltage appears at the switch node
(VSW=VOUT). As VOUT, and therefore VSW, drops, the boot-
strap capacitor voltage rises and is given by VBST = VCC
-
VOUT. When VCC-VOUT > VTH, the hi-side FET turns on again
and the switching resumes bringing the VOUT to the target
level. At that time, if the low load condition persists, the whole
cycle will repeat itself, causing a hiccup mode operation in
which VOUT fall to VCC-VTH and rises back to the target level.
This loss of regulation is undesirable in many applications.
© 2011 National Semiconductor Corporation
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