Datasheet > LH540202

LH540202

更新时间： 2024-09-29 22:33:07

品牌	Logo	应用领域
夏普 - SHARP		先进先出芯片
页数	文件大小	规格书
18页	158K
描述
CMOS 1024 x 9 Asynchronous FIFO

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LH540202 数据手册

LH540202

CMOS 1024 × 9 Asynchronous FIFO

FEATURES

FUNCTIONAL DESCRIPTION

The LH540202 is a FIFO (First-In, First-Out) memory

device, basedonfully-staticCMOS dual-portSRAMtech-

nology, capable of storing up to 1024 nine-bit words. It

follows the industry-standard architecture and package

pinouts for nine-bit asynchronous FIFOs. Each nine-bit

LH540202 word may consist of a standard eight-bit byte,

together with a parity bit or a block-marking/framing bit.

• Fast Access Times: 15/20/25/35/50 ns

• Fast-Fall-Through Time Architecture Based on

CMOS Dual-Port SRAM Technology

• Input Port and Output Port Have Entirely

Independent Timing

• Expandable in Width and Depth

• Full, Half-Full, and Empty Status Flags

• Data Retransmission Capability

• TTL-Compatible I/O

The input and output ports operate entirely inde-

pendently of each other, unless the LH540202 becomes

either totally full or else totally empty. Data flow at a port

is initiated by asserting either of two asynchronous, as-

sertive-LOWcontrol inputs:Write (W) fordata entry atthe

inputport, orRead (R) fordata retrieval atthe outputport.

• Pin and Functionally Compatible with Sharp LH5497

Full, Half-Full, and Empty status flags monitor the

extent to which the internal memory has been filled. The

system may make use of these status outputs to avoid

the risk of data loss, which otherwise might occur either

byattempting to write additional words into analready-full

LH540202, orbyattemptingto readadditionalwordsfrom

an already-empty LH540202. When an LH540202 is

operatinginadepth-cascadedconfiguration,the Half-Full

Flag is not available.

and with Am/IDT/MS7202

• Industrial Temperature Grade Option Currently

Available With Sharp LH5497H only

(Contact a Sharp Representative for More Information)

• Control Signals Assertive-LOW for Noise Immunity

• Packages:

28-Pin, 300-mil PDIP

28-Pin, 300-mil SOJ *

32-Pin PLCC

PIN CONNECTIONS

32-PIN PLCC

TOP VIEW

28-PIN PDIP

28-PIN SOJ

TOP VIEW

D₈

D₃

D₂

D₁

D₀

V_CC

D₄

D₅

D₂

D₁

D₀

D₆

D₇

FL/RT

Q₀

Q₁

Q₀

Q₁

Q₂

XO/HF

Q₇

XO/HF

Q₇

Q₆

Q₅

Q₂

Q₃

Q₆

15 16

17 18

Q₈

Q₄

V_SS

NOTE:

* = No external electrical connections are allowed.

540202-2D

540202-3D

Figure 1. Pin Connections for PDIP and

SOJ * Packages

Figure 2. Pin Connections for PLCC Package

* This is a final data sheet; except that all references to the SOJ package have Advance Information status.

12 3 4 5 6 7...18

中文翻译

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与LH540202相关器件

型号	品牌	获取价格	描述	数据表
LH540202-12	SHARP	获取价格	FIFO, 1KX9, 12ns, Asynchronous, CMOS, PDIP28,
LH540202-15	ETC	获取价格	x9 Asynchronous FIFO
LH540202-20	ETC	获取价格	x9 Asynchronous FIFO
LH540202-25	ETC	获取价格	x9 Asynchronous FIFO
LH540202-35	ETC	获取价格	x9 Asynchronous FIFO
LH540202-50	ETC	获取价格	x9 Asynchronous FIFO
LH540202-65	ETC	获取价格	x9 Asynchronous FIFO
LH540202-80	SHARP	获取价格	FIFO, 1KX9, 80ns, Asynchronous, CMOS, PDIP28, 0.600 INCH, PLASTIC, DIP-28
LH540202AK-10	SHARP	获取价格	FIFO, 1KX9, 10ns, Asynchronous, MOS, PDSO28, 0.300 INCH, PLASTIC, SOJ-28
LH540202AK-15	ETC	获取价格	x9 Asynchronous FIFO

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