Datasheet > LF9502

LF9502

更新时间： 2024-09-23 22:31:39

品牌	Logo	应用领域
逻辑 - LOGIC		/
页数	文件大小	规格书
7页	54K
描述
2K Programmable Line Buffer

阅读下载

中文翻译

获取价格

数据手册

如果您发现信息不准确，欢迎纠错

LF9502 数据手册

LF9502

DEVICES INCORPORATED

2K Programmable Line Buffer

LF9502

2K Programmable Line Buffer

DEVICES INCORPORATED

FEATURES

DESCRIPTION

The LF9502 is a high-speed, 10-bit

programmable line buffer. Some

applications the LF9502 is useful for

include sample rate conversion, data

time compression/ expansion, soft-

ware controlled data alignment, and

be programmed. Providing a delay

value on the LC10-0 inputs and driving

LCEN LOW will load the delay value

into the length control register on the

next selected clock edge. Two regis-

ters, one preceeding the program-

❑ 50 MHz Maximum Operating

Frequency

❑ Programmable Buffer Length from

2 to 2049 Clock Cycles

❑ 10-bit Data Inputs and Outputs

❑ Data Delay and Data Recirculation

programmable serial data shifting. By mable delay RAM and one following,

Modes

using the MODSEL pin, two different

modes of operation can be selected:

delay mode and data recirculation

mode. The delay mode provides a

minimum of 2 to a maximum of 2049

clock cycles of delay between the

input and output of the device. The

data recirculation mode provides a

feedback path from the data output to

the data input for use as a program-

mable circular buffer.

are included in the delay path. There-

fore, the programmed delay value

should equal the desired delay minus

2. This consequently means that the

value loaded into the length control

provide an overall range of 2 to 2049).

❑ Supports Positive or Negative Edge

System Clocks

❑ Expandable Data Word Width or

Buffer Length

❑ 44-pin PLCC, J-Lead

The active edge of the clock input,

either positive or negative edge, can

be selected with the clock select

(CLKSEL) input. All timing is based

on the active clock edge selected by

CLKSEL. Data can be held tempo-

rarily by using the clock enable

(CLKEN) input.

By using the length control input

(LC10-0) and the length control enable

(LCEN) the length of the delay buffer

or amount of recirculation delay can

LF9502 BLOCK DIAGRAM

MODSEL

LCO10-0 LCEN

DI9-0

DO9-0

CLKSEL

CLKEN

CLK

TO ALL REGISTERS

Video Imaging Products

08/16/2000–LDS.9502-G

12 3 4 5 6 7

中文翻译

下载PDF

与LF9502相关器件

型号	品牌	获取价格	描述	数据表
LF9502JC15	LOGIC	获取价格	Pipeline Register, 10-Bit, CMOS, PQCC44, PLASTIC, LCC-44
LF9502JC20	LOGIC	获取价格	2K Programmable Line Buffer
LF9502JC25	LOGIC	获取价格	2K Programmable Line Buffer
LF9502JC31	ETC	获取价格	x10 Synchronous FIFO
LF9502JC40	ETC	获取价格	x10 Synchronous FIFO
LF9502JI15	LOGIC	获取价格	Pipeline Register, 10-Bit, CMOS, PQCC44, PLASTIC, LCC-44
LF9502JI20	LOGIC	获取价格	Pipeline Register, 10-Bit, CMOS, PQCC44, PLASTIC, LCC-44
LF9502JI31	LOGIC	获取价格	Pipeline Register, 10-Bit, CMOS, PQCC44, PLASTIC, LCC-44
LF9502JI40	LOGIC	获取价格	Pipeline Register, 10-Bit, CMOS, PQCC44, PLASTIC, LCC-44
LF9520	MTRONPTI	获取价格