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LF43891JC33 PDF预览

LF43891JC33

更新时间: 2024-09-23 22:25:23
品牌 Logo 应用领域
逻辑 - LOGIC /
页数 文件大小 规格书
11页 81K
描述
9 x 9-bit Digital Filter

LF43891JC33 技术参数

是否Rohs认证: 不符合生命周期:Contact Manufacturer
零件包装代码:LCC包装说明:QCCJ, LDCC84,1.2SQ
针数:84Reach Compliance Code:compliant
ECCN代码:3A991.A.2HTS代码:8542.39.00.01
风险等级:5.34其他特性:ICC SPECIFIED @ 20MHZ
边界扫描:NO最大时钟频率:30.3 MHz
外部数据总线宽度:9JESD-30 代码:S-PQCC-J84
JESD-609代码:e0长度:29.3116 mm
低功率模式:NO湿度敏感等级:3
端子数量:84最高工作温度:70 °C
最低工作温度:输出数据总线宽度:26
封装主体材料:PLASTIC/EPOXY封装代码:QCCJ
封装等效代码:LDCC84,1.2SQ封装形状:SQUARE
封装形式:CHIP CARRIER峰值回流温度(摄氏度):225
电源:5 V认证状态:Not Qualified
座面最大高度:5.08 mm子类别:DSP Peripherals
最大压摆率:160 mA最大供电电压:5.25 V
最小供电电压:4.75 V标称供电电压:5 V
表面贴装:YES技术:CMOS
温度等级:COMMERCIAL端子面层:Tin/Lead (Sn/Pb)
端子形式:J BEND端子节距:1.27 mm
端子位置:QUAD处于峰值回流温度下的最长时间:NOT SPECIFIED
宽度:29.3116 mmuPs/uCs/外围集成电路类型:DSP PERIPHERAL, DIGITAL FILTER
Base Number Matches:1

LF43891JC33 数据手册

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LF43891  
9 x 9-bit Digital Filter  
DEVICES INCORPORATED  
FEATURES  
DESCRIPTION  
The LF43891 is a video-speed digital  
filter that contains eight filter cells  
(taps) cascaded internally and a shift-  
and-add output stage. A 9 x 9 multi-  
rate, a single LF43891 can process  
larger filter lengths by using multiple  
passes. The sampling rate can range  
from 0 to 40 MHz. Over 1000 taps  
30 MHz Maximum Sampling Rate  
320 MHz Multiply-Accumulate Rate  
8 Filter Cells  
8-bit Unsigned or 9-bit Twos  
plier, three decimation registers, and a may be processed without overflows  
Complement Data/ Coefficients  
26-bit accumulator are contained in  
each filter cell. The output stage of the  
LF43891 contains a 26-bit accumulator  
which can add the contents of any  
filter stage to the output stage accu-  
mulator shifted right by 8 bits. 8-bit  
unsigned or 9-bit twos complement  
format for data and coefficients can be  
independently selected.  
due to the architecture of the device.  
26-bit Data Outputs  
The output sample rate can be re-  
duced to one-half, one-third, or one-  
fourth the input sample rate by using  
the three decimation registers con-  
tained in every filter cell. Matrix  
multiplication, N x N spatial correla-  
tions/ convolutions, and other 2-D  
operations for image processing can  
Shift-and-Add Output Stage for  
Combining Filter Outputs  
Expandable Data Size, Coefficient  
Size, and Filter Length  
User-Selectable 2:1, 3:1, or 4:1  
Decimation  
Replaces Harris HSP43891  
84-pin PLCC, J-Lead  
Expanded coefficients and word sizes also be achieved using these registers.  
can be processed by cascading mul-  
tiple LF43891s to implement larger  
filter lengths without affecting the  
sample rate. By reducing the sample  
LF43891 BLOCK DIAGRAM  
DIENB, CIENB,  
DIN8-0  
9
ERASE, DCM1-0  
5
9
3
9
9
9
9
9
9
9
9
FILTER  
CELL 0  
FILTER  
CELL 1  
FILTER  
CELL 2  
FILTER  
CELL 3  
FILTER  
CELL 4  
FILTER  
CELL 5  
FILTER  
CELL 6  
FILTER  
CELL 7  
CIN8-0  
COUT8-0  
COENB  
ADR2-0  
26  
26  
26  
26  
26  
26  
26  
26  
MUX  
26  
SHADD  
OUTPUT  
STAGE  
SENBL  
SENBH  
RESET  
CLK  
26  
TO ALL CELLS  
TO ALL REGISTERS  
SUM25-0  
Video Imaging Products  
08/16/2000–LDS.43891-J  
1

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