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LDTA124XM3T5G PDF预览

LDTA124XM3T5G

更新时间: 2024-10-28 11:37:31
品牌 Logo 应用领域
乐山 - LRC 晶体晶体管
页数 文件大小 规格书
11页 191K
描述
Bias Resistor Transistors

LDTA124XM3T5G 技术参数

生命周期:Contact Manufacturer包装说明:,
Reach Compliance Code:unknown风险等级:5.8
最大集电极电流 (IC):0.1 A最小直流电流增益 (hFE):80
元件数量:1极性/信道类型:PNP
最大功率耗散 (Abs):0.6 W子类别:BIP General Purpose Small Signal
表面贴装:YES晶体管元件材料:SILICON
Base Number Matches:1

LDTA124XM3T5G 数据手册

 浏览型号LDTA124XM3T5G的Datasheet PDF文件第2页浏览型号LDTA124XM3T5G的Datasheet PDF文件第3页浏览型号LDTA124XM3T5G的Datasheet PDF文件第4页浏览型号LDTA124XM3T5G的Datasheet PDF文件第5页浏览型号LDTA124XM3T5G的Datasheet PDF文件第6页浏览型号LDTA124XM3T5G的Datasheet PDF文件第7页 
LESHAN RADIO COMPANY, LTD.  
Bias Resistor Transistors  
PNP Silicon Surface Mount Transistors  
LDTA114EM3T5G  
Series  
With Monolithic Bias Resistor Network  
This new series of digital transistors is designed to replace a single  
device and its external resistor bias network. The BRT (Bias Resistor  
Transistor) contains a single transistor with a monolithic bias network  
consisting of two resistors; a series base resistor and a base-emitter  
resistor. The BRT eliminates these individual components by integrating  
them into a single device. The use of a BRT can reduce both system  
cost and board space. The device is housed in the SOT-723 package  
which is designed for low power surface mount applications.  
ƽSimplifies Circuit Design  
3
2
1
SOT-723  
ƽReduces Board Space  
ƽReduces Component Count  
PIN 3  
COLLECTOR  
(OUTPUT)  
ƽThe SOT-723 Package can be Soldered using Wave or Reflow.  
ƽAvailable in 4 mm, 8000 Unit Tape & Reel  
PIN 1  
BASE  
(INPUT)  
R
R
1
ƽThese are Pb-Free Devices.  
2
PIN 2  
EMITTER  
(GROUND)  
MAXIMUM RATINGS (T = 25°C unless otherwise noted)  
A
Rating  
Collector-Base Voltage  
Collector-Emitter Voltage  
Collector Current  
Symbol  
Value  
50  
Unit  
Vdc  
V
CBO  
CEO  
MARKING DIAGRAM  
V
50  
Vdc  
I
C
100  
mAdc  
3
THERMAL CHARACTERISTICS  
Characteristic  
XX M  
Symbol  
Max  
Unit  
Total Device Dissipation  
P
260 (Note 1)  
600 (Note 2)  
2.0 (Note 1)  
4.8 (Note 2)  
mW  
2
1
D
T = 25°C  
A
mW/°C  
°C/W  
°C  
Derate above 25°C  
xx = Specific Device Code  
M
= Date Code  
Thermal Resistance –  
Junction-to-Ambient  
R
480 (Note 1)  
205 (Note 2)  
θ
JA  
Junction and Storage  
Temperature Range  
T
–55 to +150  
J, Tstg  
1. FR–4 @ Minimum Pad  
2. FR–4 @ 1.0 x 1.0 inch Pad  
Version 1.0  
LDTA114EM3T5G_S-1/11  

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