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LC78625 PDF预览

LC78625

更新时间: 2024-09-22 22:37:07
品牌 Logo 应用领域
三洋 - SANYO /
页数 文件大小 规格书
35页 436K
描述
Compact Disc Player DSP

LC78625 数据手册

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Ordering number : EN5502  
CMOS LSI  
LC78625E  
Compact Disc Player DSP  
• Demodulated EFM signal buffering in internal RAM to  
handle up to ±4 frames of disc rotational jitter  
• Demodulated EFM signal reordering in the prescribed  
order for data unscrambling and de-interleaving  
• Error detection, correction, and flag processing (error  
correction scheme: dual C1 plus dual C2 correction)  
• The LC78625E sets the C2 flags based on the C1 flags  
and a C2 check, and then performs signal interpolation  
or muting depending on the C2 flags. The interpolation  
circuit uses a quadruple interpolation scheme. The  
output value converges to the muting level when four or  
more consecutive C2 flags occur.  
Overview  
The LC78625E is a CMOS LSI that implements the signal  
processing and servo control required by compact disc  
players, laser discs, CD-V, CD-I and related products. The  
LC78625E provides several types of signal processing,  
including demodulation of the optical pickup EFM signal,  
de-interleaving, error detection and correction, and digital  
filters that can help reduce the cost of CD player units. It  
also processes a rich set of servo system commands sent  
from the control microprocessor. It also incorporates an  
EFM-PLL circuit and a one-bit D/A converter.  
This LSI is an improved version of the LC78620E. In  
addition to supporting low-voltage operation, on/off  
control of the de-emphasis function and use of the  
bilingual function have been enabled in certain additional  
modes.  
Package Dimensions  
unit: mm  
3174-QFP80E  
[LC78625E]  
Functions  
• The LC78625E takes an HF signal as input, digitizes  
(slices) that signal at a precise level, converts that signal  
to an EFM signal, and generates a PLL clock with an  
average frequency of 4.3218 MHz by comparing the  
phases of that signal and an internal VCO.  
• A precise reference clock and the necessary internal  
timings are generated using an external 16.9344 MHz  
crystal oscillator.  
• Disc motor speed control using a frame phase difference  
signal generated from the playback clock and the  
reference clock  
• Frame synchronization signal detection, protection, and  
interpolation to assure stable data readout  
• EFM signal demodulation and conversion to 8-bit  
symbol data  
SANYO: QFP80E  
• Subcode data separation from the EFM demodulated  
signal and output of that data to an external  
microprocessor  
• Subcode Q signal output (LSB first) to a microprocessor  
over the serial interface after performing a CRC error  
check  
SANYO Electric Co.,Ltd. Semiconductor Bussiness Headquarters  
TOKYO OFFICE Tokyo Bldg., 1-10, 1 Chome, Ueno, Taito-ku, TOKYO, 110 JAPAN  
22897HA (OT) No. 5502-1/35  

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