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LC4384B-35F256I PDF预览

LC4384B-35F256I

更新时间: 2024-11-29 09:29:27
品牌 Logo 应用领域
莱迪思 - LATTICE 可编程逻辑
页数 文件大小 规格书
59页 1407K
描述
EE PLD, 4.5ns, 384-Cell, CMOS, PBGA256,

LC4384B-35F256I 技术参数

是否无铅: 含铅是否Rohs认证: 不符合
生命周期:ObsoleteReach Compliance Code:compliant
ECCN代码:EAR99HTS代码:8542.39.00.01
风险等级:5.92其他特性:YES
系统内可编程:YESJESD-30 代码:S-PBGA-B256
JESD-609代码:e0JTAG BST:YES
湿度敏感等级:3宏单元数:384
端子数量:256封装主体材料:PLASTIC/EPOXY
封装代码:BGA封装等效代码:BGA256,16X16,40
封装形状:SQUARE封装形式:GRID ARRAY
峰值回流温度(摄氏度):225电源:1.8/3.3,2.5 V
可编程逻辑类型:EE PLD传播延迟:4.5 ns
认证状态:Not Qualified子类别:Programmable Logic Devices
表面贴装:YES技术:CMOS
端子面层:Tin/Lead (Sn63Pb37)端子形式:BALL
端子节距:1 mm端子位置:BOTTOM
处于峰值回流温度下的最长时间:NOT SPECIFIED

LC4384B-35F256I 数据手册

 浏览型号LC4384B-35F256I的Datasheet PDF文件第2页浏览型号LC4384B-35F256I的Datasheet PDF文件第3页浏览型号LC4384B-35F256I的Datasheet PDF文件第4页浏览型号LC4384B-35F256I的Datasheet PDF文件第5页浏览型号LC4384B-35F256I的Datasheet PDF文件第6页浏览型号LC4384B-35F256I的Datasheet PDF文件第7页 
TM  
ispMACH 4000V/B/C Family  
3.3V/2.5V/1.8V In-System Programmable  
TM  
SuperFAST High Density PLDs  
July 2002  
Data Sheet  
Broad Device Offering  
• 32 to 512 macrocells  
• 30 to 208 I/O pins  
Features  
High Performance  
• f  
= 400MHz maximum operating frequency  
MAX  
• 44 to 256 pins/balls in TQFP or fpBGA packages  
• Commercial and industrial temperature ranges  
• t = 2.5ns propagation delay  
PD  
• Up to four global clock pins with programmable  
clock polarity control  
Easy System Integration  
• Operation with 3.3V, 2.5V or 1.8V LVCMOS I/O  
• Operation with 3.3V (4000V), 2.5V (4000B) or  
1.8V (4000C) supplies  
• Up to 80 PTs per output  
Ease of Design  
• Enhanced macrocells with individual clock,  
reset, preset and clock enable controls  
• Up to four global OE controls  
• Hot-socketing  
• Open-drain capability  
• Input pull-up, pull-down or bus-keeper  
• Programmable output slew rate  
• 3.3V PCI compatible  
• Individual local OE control per I/O pin  
• Excellent First-Time-FitTM and ret  
• Fast path, SpeedLockingTM Path, and wide-PT  
path  
• IEEE 1149.1 boundary scan testable  
• 3.3V/2.5V/1.8V In-System Programmable  
(ISP™) using IEEE 1532 compliant interface  
• I/O pins with fast setup path  
• Wide input gating (36 input logic blocks) for fast  
counters, state machines and address decoders  
Low Power  
• 1.8V core E2CMOS® technology  
• CMOS design techniques provide low static and  
dynamic power  
Table 1. ispMACH 4000V/B/C Family Selection Guide  
ispMACH  
ispMACH  
ispMACH  
ispMACH  
ispMACH  
ispMACH  
4032V/B/C  
4064V/B/C  
4128V/B/C  
4256V/B/C  
4384V/B/C  
4512V/B/C  
Macrocells  
User I/O Options  
32  
30/32  
2.5  
64  
30/32/64  
2.5  
128  
64/92  
2.7  
256  
64/128/160  
3.0  
384  
128/192  
3.5  
512  
128/208  
3.5  
t
(ns)  
PD  
t (ns)  
1.8  
1.8  
1.8  
2.0  
2.0  
2.0  
S
t
f
(ns)  
2.2  
400  
2.2  
400  
2.7  
333  
2.7  
322  
2.7  
322  
2.7  
322  
CO  
(MHz)  
MAX  
Supply Voltages (V)  
Pins/Package  
3.3/2.5/1.8V  
3.3/2.5/1.8V  
3.3/2.5/1.8V  
3.3/2.5/1.8V  
3.3/2.5/1.8V  
3.3/2.5/1.8V  
44 TQFP  
44 TQFP  
48 TQFP  
100 TQFP  
48 TQFP  
100 TQFP  
128 TQFP  
100 TQFP  
176 TQFP  
176 TQFP  
256 fpBGA  
176 TQFP  
256 fpBGA  
256 fpBGA*  
*128-I/O and 160-I/O congurations.  
www.latticesemi.com  
1
ispm4k_10  

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