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GAL16V8B-10LPI PDF预览

GAL16V8B-10LPI

更新时间： 2024-02-16 01:38:10
品牌 Logo 应用领域
莱迪思 - LATTICE 可编程逻辑器件光电二极管输入元件时钟
页数 文件大小 规格书
23页 395K
描述
High Performance E2CMOS PLD Generic Array Logic

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GAL16V8B-10LPI 技术参数

是否Rohs认证： 不符合生命周期：Obsolete
零件包装代码：DIP包装说明：PLASTIC, DIP-20
针数：20Reach Compliance Code：not_compliant
ECCN代码：EAR99HTS代码：8542.39.00.01
风险等级：5.55Is Samacsys：N
其他特性：REGISTER PRELOAD; POWER-UP RESET架构：PAL-TYPE
最大时钟频率：58.8 MHzJESD-30 代码：R-PDIP-T20
JESD-609代码：e0长度：26.125 mm
专用输入次数：8I/O 线路数量：8
输入次数：18输出次数：8
产品条款数：64端子数量：20
最高工作温度：85 °C最低工作温度：-40 °C
组织：8 DEDICATED INPUTS, 8 I/O输出函数：MACROCELL
封装主体材料：PLASTIC/EPOXY封装代码：DIP
封装等效代码：DIP20,.3封装形状：RECTANGULAR
封装形式：IN-LINE电源：5 V
可编程逻辑类型：EE PLD传播延迟：10 ns
认证状态：Not Qualified座面最大高度：4.57 mm
子类别：Programmable Logic Devices最大供电电压：5.5 V
最小供电电压：4.5 V标称供电电压：5 V
表面贴装：NO技术：CMOS
温度等级：INDUSTRIAL端子面层：Tin/Lead (Sn/Pb)
端子形式：THROUGH-HOLE端子节距：2.54 mm
端子位置：DUAL宽度：7.62 mm
Base Number Matches：1

GAL16V8B-10LPI 数据手册

 浏览型号GAL16V8B-10LPI的Datasheet PDF文件第2页浏览型号GAL16V8B-10LPI的Datasheet PDF文件第3页浏览型号GAL16V8B-10LPI的Datasheet PDF文件第4页浏览型号GAL16V8B-10LPI的Datasheet PDF文件第5页浏览型号GAL16V8B-10LPI的Datasheet PDF文件第6页浏览型号GAL16V8B-10LPI的Datasheet PDF文件第7页 
GAL16V8  
High Performance E2CMOS PLD  
Generic Array Logic™  
FUNCTIONAL BLOCK DIAGRAM  
FEATURES  
• HIGH PERFORMANCE E2CMOS® TECHNOLOGY  
— 5 ns Maximum Propagation Delay  
— Fmax = 166 MHz  
I/CLK  
CLK  
— 4 ns Maximum from Clock Input to Data Output  
— UltraMOS® Advanced CMOS Technology  
I/O/Q  
I/O/Q  
I/O/Q  
I/O/Q  
I/O/Q  
I/O/Q  
I/O/Q  
8
8
OLMC  
I
I
I
I
I
I
I
I
• 50% to 75% REDUCTION IN POWER FROM BIPOLAR  
— 75mA Typ Icc on Low Power Device  
— 45mA Typ Icc on Quarter Power Device  
OLMC  
OLMC  
OLMC  
OLMC  
OLMC  
OLMC  
OLMC  
• ACTIVE PULL-UPS ON ALL PINS  
• E2 CELL TECHNOLOGY  
— Reconfigurable Logic  
— Reprogrammable Cells  
— 100% Tested/Guaranteed 100% Yields  
— High Speed Electrical Erasure (<100ms)  
— 20 Year Data Retention  
8
8
8
8
8
8
• EIGHT OUTPUT LOGIC MACROCELLS  
— Maximum Flexibility for Complex Logic Designs  
— Programmable Output Polarity  
— Also Emulates 20-pin PAL® Devices with Full Func-  
tion/Fuse Map/Parametric Compatibility  
• PRELOAD AND POWER-ON RESET OF ALL REGISTERS  
— 100% Functional Testability  
• APPLICATIONS INCLUDE:  
— DMA Control  
— State Machine Control  
— High Speed Graphics Processing  
— Standard Logic Speed Upgrade  
I/O/Q  
I/OE  
OE  
• ELECTRONIC SIGNATURE FOR IDENTIFICATION  
DESCRIPTION  
PIN CONFIGURATION  
The GAL16V8C, at 5 ns maximum propagation delay time, com-  
bines a high performance CMOS process with Electrically Eras-  
able (E2) floating gate technology to provide the highest speed  
performance available in the PLD market. High speed erase times  
(<100ms) allow the devices to be reprogrammed quickly and ef-  
ficiently.  
DIP  
1
20  
Vcc  
I/CLK  
PLCC  
I/O/Q  
I/O/Q  
I/O/Q  
I/O/Q  
I/O/Q  
I/O/Q  
I/O/Q  
I/O/Q  
I/OE  
I
I
I
I/CLK Vcc I/O/Q  
20  
I
I
2
The generic architecture provides maximum design flexibility by  
allowing the Output Logic Macrocell (OLMC) to be configured by  
the user. An important subset of the many architecture configu-  
rations possible with the GAL16V8 are the PAL architectures  
listed in the table of the macrocell description section. GAL16V8  
devices are capable of emulating any of these PAL architectures  
with full function/fuse map/parametric compatibility.  
GAL  
18  
I/O/Q  
4
6
I
16V8  
I/O/Q  
I/O/Q  
I
GAL16V8  
Top View  
5
I
I
16  
I
15  
I/O/Q  
I/O/Q  
I
I
I
14  
I
8
9
I
11  
13  
Unique test circuitry and reprogrammable cells allow complete  
AC, DC, and functional testing during manufacture. As a result,  
Lattice Semiconductor guarantees 100% field programmability  
and functionality of all GAL products. In addition, 100 erase/write  
cycles and data retention in excess of 20 years are guaranteed.  
GND I/OE I/O/Q I/O/Q  
I
10  
11  
GND  
2
Copyright © 1996 Lattice Semiconductor Corporation. E CMOS, GAL, ispGAL, ispLSI, pLSI, pDS, Silicon Forest, UltraMOS, L with Lattice Semiconductor Corp. and L (Stylized) are registered  
trademarks of Lattice Semiconductor Corporation (LSC). The LSC Logo, Generic Array Logic, In-System Programmability, In-System Programmable, ISP, ispATE, ispCODE, ispDOWNLOAD,  
ispGDS, ispStarter, ispSTREAM, ispTEST, ispTURBO, Latch-Lock, pDS+, RFT, Total ISP and Twin GLB are trademarks of Lattice Semiconductor Corporation. ISP is a service mark of Lattice  
Semiconductor Corporation. All brand names or product names mentioned are trademarks or registered trademarks of their respective holders.  
LATTICE SEMICONDUCTOR CORP., 5555 Northeast Moore Ct., Hillsboro, Oregon 97124, U.S.A.  
1996 Data Book  
Tel. (503) 681-0118; 1-888-ISP-PLDS; FAX (503) 681-3037; http://www.lattice.com  
1234567...23

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