Datasheet > L9218A

L9218A

更新时间： 2024-09-27 22:31:39

品牌	Logo	应用领域
杰尔 - AGERE		/
页数	文件大小	规格书
30页	365K
描述
Low-Cost Line Interface

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L9218A 数据手册

Data Sheet

November 2001

L9218A/G Low-Cost Line Interface

Features

Description

■ Basic forward battery only SLIC functionality at a

This general-purpose electronic subscriber loop

low cost

interface circuit (SLIC) is optimized for low cost, while

still providing a satisfactory set of features.

■ Pin compatible with Agere Systems Inc. L9219 and

L9217 SLIC

The L9218 is pin-for-pin compatible with the Agere

L9219 and L9217 SLICs.

■ Low active power (typical 138 mW during on-hook

transmission)

The L9218 requires a 5 V power supply and single

battery to operate. This is a forward battery only

device. Additionally, a low-power scan mode,

wherein all circuitry except the off-hook supervision is

shut down to conserve power, is available.

■ Low-power scan mode for low-power, on-hook

power dissipation (59 mW typical)

■ Minimal external components

■ Distortion-free, on-hook transmission

Via the logic inputs, a low or high current limit may be

selected. The low value is set via a single external

resistor, and the high value is 1.4 times the low value.

■ Convenient operating states:

— Forward battery low current limit

— Forward battery high current limit

— Low-power scan

Device overhead is fixed and is adequate for

3.14 dBm into 900 Ω of on-hook transmission.

— Disconnect (high impedance)

Both the loop supervision and ring trip supervision

functions are offered with user-controlled thresholds

via external resistors.

■ Adjustable supervision functions:

— Off-hook detector with hysteresis

— Ring trip detector

The L9218 is offered with a receive gain that is opti-

mized for interface to a first-generation type codec

(L9218A). It is also offered with a gain option that is

optimized for interface to a third- or fourth-generation

type codec (L9218G). In both cases, minimizing

external components required at this interface. In the

receive direction, the device may be dc-coupled to a

third-generation codec. No dc blocking capacitors

are needed.

■ Logic controlled high and low current limit

■ Two gain options to optimize the codec interface

■ Thermal protection with thermal shutdown indica-

tion

Data control is via a parallel data control scheme.

The device is available in a 28-pin PLCC package. It

is built by using a 90 V complementary bipolar

(CBIC) process.

12 3 4 5 6 7...30

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