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L8C204MMB40 PDF预览

L8C204MMB40

更新时间: 2024-01-09 18:43:48
品牌 Logo 应用领域
逻辑 - LOGIC 内存集成电路先进先出芯片时钟
页数 文件大小 规格书
22页 182K
描述
512/1K/2K/4K x 9-bit Asynchronous FIFO

L8C204MMB40 技术参数

是否Rohs认证:不符合生命周期:Obsolete
包装说明:DFP, FL28(UNSPEC)Reach Compliance Code:unknown
风险等级:5.92Is Samacsys:N
最长访问时间:40 ns最大时钟频率 (fCLK):20 MHz
JESD-30 代码:R-XDFP-F28JESD-609代码:e0
内存密度:36864 bit内存集成电路类型:OTHER FIFO
内存宽度:9湿度敏感等级:3
端子数量:28字数:4096 words
字数代码:4000工作模式:ASYNCHRONOUS
最高工作温度:125 °C最低工作温度:-55 °C
组织:4KX9封装主体材料:CERAMIC
封装代码:DFP封装等效代码:FL28(UNSPEC)
封装形状:RECTANGULAR封装形式:FLATPACK
电源:5 V认证状态:Not Qualified
筛选级别:38535Q/M;38534H;883B最大待机电流:0.005 A
子类别:FIFOs最大压摆率:0.09 mA
标称供电电压 (Vsup):5 V表面贴装:YES
技术:CMOS温度等级:MILITARY
端子面层:Tin/Lead (Sn/Pb)端子形式:FLAT
端子位置:DUALBase Number Matches:1

L8C204MMB40 数据手册

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L8C201/202/203/204  
512/1K/2K/4K x 9-bit Asynchronous FIFO  
DEVICES INCORPORATED  
FEATURES  
DESCRIPTION  
The L8C201, L8C202, L8C203, and  
L8C204 are dual-port First-In/ First-  
Out (FIFO) memories. The FIFO  
memory products are organized as:  
The read and write operations are  
internally sequential through the use  
of ring pointers. No address informa-  
tion is required to load and unload  
data. The write operation occurs  
when the Write (W) signal is LOW.  
Read occurs when Read (R) goes  
LOW. The nine data outputs go to the  
high impedance state when R is  
HIGH. Retransmit (RT) capability  
allows for reset of the read pointer  
when RT is pulsed LOW, allowing for  
retransmission of data from the  
beginning. Read Enable (R) and Write  
Enable (W) must both be HIGH  
during a retransmit cycle, and then R  
is used to access the data. A Half-Full  
(HF) output flag is available in the  
single device and width expansion  
modes. In the depth expansion  
First-In/ First-Out (FIFO) using  
Dual-Port Memory  
Advanced CMOS Technology  
High Speed — to 10 ns Access Time  
Asynchronous and Simultaneous  
L8C201 — 512 x 9-bit  
L8C202 — 1024 x 9-bit  
L8C203 — 2048 x 9-bit  
L8C204 — 4096 x 9-bit  
Read and Write  
Fully Expandable by both Word  
Depth and/ or Bit Width  
Each device utilizes a special algorithm  
that loads and empties data on a first-  
in/ first-out basis. Full and Empty flags  
are provided to prevent data overflow  
and underflow. Three additional pins  
are also provided to allow for unlimited  
expansion in both word size and depth.  
Depth Expansion does not result in a  
flow-through penalty. Multiple devices  
are connected with the data and control  
signals in parallel. The active device is  
determined by the Expansion In (XI)  
and Expansion Out (XO) signals which  
are daisy chained from device to  
Empty and Full Warning Flags  
Half-Full Flag Capability  
Auto Retransmit Capability  
Package Styles Available:  
• 28-pin Plastic DIP  
• 32-pin Plastic LCC  
• 28-pin Ceramic Flatpack  
configuration, this pin provides the  
Expansion Out (XO) information  
which is used to tell the next FIFO that  
it will be activated.  
device.  
L8C201/202/203/204 BLOCK DIAGRAM  
These FIFOs are designed to have the  
fastest data access possible. Even in  
lower cycle time applications, faster  
access time can eliminate timing  
bottlenecks as well as leave enough  
margin to allow the use of the devices  
without external bus drivers.  
DATA INPUTS  
D8-0  
9
WRITE  
CONTROL  
W
RAM ARRAY  
512 x 9-bit  
1K x 9-bit  
WRITE  
POINTER  
READ  
POINTER  
The FIFOs are designed for those  
applications requiring asychronous  
and simultaneous read/ writes in  
multiprocessing and rate buffer  
applications.  
2K x 9-bit  
4K x 9-bit  
THREE-STATE  
BUFFERS  
DATA OUTPUTS  
Q
8-0  
READ  
CONTROL  
R
RS  
RESET  
LOGIC  
FL/RT  
FLAG  
LOGIC  
EF  
FF  
EXPANSION  
LOGIC  
XI  
XO/HF  
FIFO Products  
03/04/99–LDS.8C201/2/3/4-H  
1

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