L8C201/202/203/204
DEVICES INCORPORATED
512/1K/2K/4K x 9-bit Asynchronous FIFO
L8C201/202/203/204
512/1K/2K/4K x 9-bit Asynchronous FIFO
DEVICES INCORPORATED
FEATURES
DESCRIPTION
The L8C201, L8C202, L8C203, and
L8C204 are dual-port First-In/ First-
Out (FIFO) memories. The FIFO
memory products are organized as:
The read and write operations are
internally sequential through the use
of ring pointers. No address informa-
tion is required to load and unload
data. The write operation occurs
when the Write (W) signal is LOW.
Read occurs when Read (R) goes
LOW. The nine data outputs go to the
high impedance state when R is
HIGH. Retransmit (RT) capability
allows for reset of the read pointer
when RT is pulsed LOW, allowing for
retransmission of data from the
beginning. Read Enable (R) and Write
Enable (W) must both be HIGH
during a retransmit cycle, and then R
is used to access the data. A Half-Full
(HF) output flag is available in the
single device and width expansion
modes. In the depth expansion
❑ First-In/ First-Out (FIFO) using
Dual-Port Memory
❑ Advanced CMOS Technology
❑ High Speed — to 10 ns Access Time
❑ Asynchronous and Simultaneous
L8C201 — 512 x 9-bit
L8C202 — 1024 x 9-bit
L8C203 — 2048 x 9-bit
L8C204 — 4096 x 9-bit
Read and Write
❑ Fully Expandable by both Word
Depth and/ or Bit Width
Each device utilizes a special algorithm
that loads and empties data on a first-
in/ first-out basis. Full and Empty flags
are provided to prevent data overflow
and underflow. Three additional pins
are also provided to allow for unlimited
expansion in both word size and depth.
Depth Expansion does not result in a
flow-through penalty. Multiple devices
are connected with the data and control
signals in parallel. The active device is
determined by the Expansion In (XI)
and Expansion Out (XO) signals which
are daisy chained from device to
❑ Empty and Full Warning Flags
❑ Half-Full Flag Capability
❑ Auto Retransmit Capability
❑ Package Styles Available:
• 28-pin Plastic DIP
• 32-pin Plastic LCC
• 28-pin Ceramic Flatpack
configuration, this pin provides the
Expansion Out (XO) information
which is used to tell the next FIFO that
it will be activated.
device.
L8C201/202/203/204 BLOCK DIAGRAM
These FIFOs are designed to have the
fastest data access possible. Even in
lower cycle time applications, faster
access time can eliminate timing
bottlenecks as well as leave enough
margin to allow the use of the devices
without external bus drivers.
DATA INPUTS
D8-0
9
WRITE
CONTROL
W
RAM ARRAY
512 x 9-bit
1K x 9-bit
WRITE
POINTER
READ
POINTER
The FIFOs are designed for those
applications requiring asychronous
and simultaneous read/ writes in
multiprocessing and rate buffer
applications.
2K x 9-bit
4K x 9-bit
THREE-STATE
BUFFERS
DATA OUTPUTS
Q
8-0
READ
CONTROL
R
RS
RESET
LOGIC
FL/RT
FLAG
LOGIC
EF
FF
EXPANSION
LOGIC
XI
XO/HF
FIFO Products
03/04/99–LDS.8C201/2/3/4-H
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