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L7C185MMB12L PDF预览

L7C185MMB12L

更新时间： 2024-11-26 21:18:31
品牌 Logo 应用领域
逻辑 - LOGIC 静态存储器内存集成电路
页数 文件大小 规格书
8页 306K
描述
Standard SRAM, 8KX8, 12ns, CMOS, CDFP28, CERAMIC, FP-28

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L7C185MMB12L 技术参数

是否Rohs认证： 不符合生命周期：Obsolete
零件包装代码：DFP包装说明：DFP,
针数：28Reach Compliance Code：unknown
ECCN代码：3A001.A.2.CHTS代码：8542.32.00.41
风险等级：5.88最长访问时间：12 ns
JESD-30 代码：R-CDFP-F28长度：18.542 mm
内存密度：65536 bit内存集成电路类型：STANDARD SRAM
内存宽度：8湿度敏感等级：3
功能数量：1端子数量：28
字数：8192 words字数代码：8000
工作模式：ASYNCHRONOUS最高工作温度：125 °C
最低工作温度：-55 °C组织：8KX8
封装主体材料：CERAMIC, METAL-SEALED COFIRED封装代码：DFP
封装形状：RECTANGULAR封装形式：FLATPACK
并行/串行：PARALLEL认证状态：Not Qualified
座面最大高度：2.286 mm最大供电电压 (Vsup)：5.5 V
最小供电电压 (Vsup)：4.5 V标称供电电压 (Vsup)：5 V
表面贴装：YES技术：CMOS
温度等级：MILITARY端子形式：FLAT
端子节距：1.27 mm端子位置：DUAL
宽度：9.017 mmBase Number Matches：1

L7C185MMB12L 数据手册

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L7C185  
8K x 8 Static RAM (Low Power)  
DEVICES INCORPORATED  
FEATURES  
DESCRIPTION  
The L7C185 is a high-performance,  
low-power CMOS static RAM. The  
storage circuitry is organized as 8,192  
as 2 V. The L7C185 and L7CL185-L  
consume only 30 µW and 15 µW  
(typical) respectively at 3 V, allowing  
q 8K x 8 Static RAM with Chip Select  
Powerdown, Output Enable  
q Auto-Powerdown™ Design  
q Advanced CMOS Technology  
q High Speed — to 12 ns maximum  
q Low Power Operation  
Active:  
words by 8 bits per word. The 8 Data effective battery backup operation.  
In and Data Out signals share I/O  
The L7C185 provides asynchronous  
pins. These devices are available in  
(unclocked) operation with matching  
four speeds with maximum access  
access and cycle times. Two Chip  
times from 12 ns to 25 ns.  
Enables (one active-low) and a three-  
425 mW typical at 25 ns  
Standby (typical):  
400µW (L7C185)  
200 µW (L7C185-L)  
Inputs and outputs are TTL compat-  
ible. Operation is from a single +5 V  
power supply. Power consumption  
for the L7C185 is 425 mW (typical) at  
25 ns. Dissipation drops to 60 mW  
(typical) for the L7C185 and 50 mW  
(typical) for the L7C185-L when the  
memory is deselected.  
state I/O bus with a separate Output  
Enable control simplify the connection  
of several chips for increased storage  
capacity.  
q Data Retention at 2 V for Battery  
Backup Operation  
Memory locations are specified on  
address pins A0 through A12. Read-  
ing from a designated location is  
accomplished by presenting an  
address and driving CE1 and OE  
LOW, and CE2 and WE HIGH. The  
data in the addressed memory  
location will then appear on the Data  
Out pins within one access time. The  
output pins stay in a high-impedance  
state when CE1 or OE is HIGH, or CE2  
or WE is LOW.  
q DESC SMD No. 5962-38294  
q Available 100% Screened to  
MIL-STD-883, Class B  
Two standby modes are available.  
Proprietary Auto-Powerdown™  
circuitry reduces power consumption  
automatically during read or write  
accesses which are longer than the  
minimum access time, or when the  
memory is deselected. In addition,  
data may be retained in inactive  
storage with a supply voltage as low  
q Plug Compatible with IDT7164,  
Cypress CY7C185/186  
q Package Styles Available:  
• 28-pin Plastic DIP  
• 28-pin Ceramic DIP  
• 28-pin Plastic SOJ  
• 28-pin Ceramic Flatpack  
• 28-pin Ceramic LCC  
• 32-pin Ceramic LCC  
Writing to an addressed location is  
accomplished when the active-low  
CE1 and WE inputs are both LOW,  
and CE2 is HIGH. Any of these  
signals may be used to terminate the  
write operation. Data In and Data Out  
signals have the same polarity.  
L7C185 BLOCK DIAGRAM  
Latchup and static discharge pro-  
tection are provided on-chip. The  
L7C185 can withstand an injection  
current of up to 200 mA on any pin  
without damage.  
256 x 32 x 8  
MEMORY  
ARRAY  
8
ROW  
ADDRESS  
CE  
CE  
WE  
OE  
1
2
8
COLUMN SELECT  
I/O7-0  
CONTROL  
& COLUMN SENSE  
OBSOLETE  
5
COLUMN ADDRESS  
64K Static RAMs  
07/07/1999–LDS.185-E  
1
12345678

中文翻译

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