Datasheet > L74VHC1GT32DFT2

L74VHC1GT32DFT2

更新时间： 2024-02-26 10:35:04

品牌	Logo	应用领域
乐山 - LRC		栅
页数	文件大小	规格书
6页	191K
描述
2-Input OR Gate with LSTTL-Compatible Inputs

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L74VHC1GT32DFT2 数据手册

LESHAN RADIO COMPANY, LTD.

2-Input OR Gate

with LSTTL–Compatible Inputs

L74VHC1GT32

The L74VHC1GT32 is an advanced high speed CMOS 2–input OR gate fabricated with silicon gate CMOS technology. It achieves

high speed operation similar to equivalent Bipolar Shortly TTL while maintaining CMOS low power dissipation.

The internal circuit is composed of three stages, including an open drain output which provides the ability to set output switching level.

This allows the L74VHC1GT32 to be used to interface 5 V circuits to circuits of any voltage between V _CCand 7 V using an external

resistor and power supply.

The device input is compatible with TTL–type input thresholds and the output has a full 5.0 V CMOS level output swing. The input

protection circuitry on this device allows overvoltage tolerance on the input, allowing the device to be used as a logic–level translator from

3.0 V CMOS logic to 5.0 V CMOS Logic or from 1.8 V CMOS logic to 3.0 V CMOS Logic while operating at the high–voltage power

supply.

The L74VHC1GT32 input structure provides protection when voltages up to 7 V are applied, regardless of the supply voltage. This

allows the L74VHC1GT32 to be used to interface 5 V circuits to 3 V circuits. The output structures also provide protection when

V _CC= 0 V. These input and output structures help prevent device destruction caused by supply voltage – input/output voltage mismatch,

battery backup, hot insertion, etc.

• High Speed: t _PD= 3.7 ns (Typ) at V _CC= 5 V

• Low Power Dissipation: I _CC= 2 mA (Max) at T _A= 25°C

• Power Down Protection Provided on Inputs

• Balanced Propagation Delays

• Pin and Function Compatible with Other Standard Logic Families

• Chip Complexity: FETs = 60; Equivalent Gates = 15

MARKING DIAGRAMS

V4^d

SC–70/SC–88A/SOT–353

DF SUFFIX

Pin 1

d = Date Code

Figure 1. Pinout (Top View)

V4^d

Figure 2. Logic Symbol

SOT–23/TSOP–5/SC–59

DT SUFFIX

Pin 1

d = Date Code

FUNCTION TABLE

PIN ASSIGNMENT

Inputs

Output

IN B

IN A

GND

OUT Y

V _CC

ORDERING INFORMATION

See detailed ordering and shipping information in the

package dimensions section on page 5 of this data sheet.

1/6

12 3 4 5 6

中文翻译

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与L74VHC1GT32DFT2相关器件

型号	品牌	获取价格	描述	数据表
L74VHC1GT32DFT4	LRC	获取价格	2-Input OR Gate with LSTTL-Compatible Inputs
L74VHC1GT32DTT1	LRC	获取价格	2-Input OR Gate with LSTTL-Compatible Inputs
L74VHC1GT32DTT3	LRC	获取价格	2-Input OR Gate with LSTTL-Compatible Inputs
L74VHC1GT50	LRC	获取价格	Noninverting Buffer / CMOS Logic Level Shifter
L74VHC1GT50DFT1	LRC	获取价格	Noninverting Buffer / CMOS Logic Level Shifter
L74VHC1GT50DFT2	LRC	获取价格	Noninverting Buffer / CMOS Logic Level Shifter
L74VHC1GT50DFT4	LRC	获取价格	Noninverting Buffer / CMOS Logic Level Shifter
L74VHC1GT50DTT1	LRC	获取价格	Noninverting Buffer / CMOS Logic Level Shifter
L74VHC1GT50DTT3	LRC	获取价格	Noninverting Buffer / CMOS Logic Level Shifter
L74VHC1GU04	LRC	获取价格	advanced high speed CMOS Unbuffered inverter fabricated with silicon gate CMOS technology

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