Datasheet > L74VHC1GT14DFT1

L74VHC1GT14DFT1

更新时间： 2024-09-27 05:41:19

品牌	Logo	应用领域
乐山 - LRC		转换器电平转换器触发器
页数	文件大小	规格书
6页	326K
描述
Schmitt-Trigger Inverter/ CMOS Logic Level Shifter with LSTTL-Compatible Inputs

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L74VHC1GT14DFT1 数据手册

LESHAN RADIO COMPANY, LTD.

Schmitt-Trigger Inverter/ CMOS Logic Level Shifter

with LSTTL–Compatible Inputs

L74VHC1GT14

The L74VHC1GT14 is a single gate CMOS Schmitt–trigger inverter fabricated with silicon gate CMOS technology. It achieves high

speed operation similar to equivalent Bipolar Schottky TTL while maintaining CMOS low power dissipation.

The internal circuit is composed of three stages, including a buffer output which provides high noise immunity and stable output.

The device input is compatible with TTL–type input thresholds and the output has a full 5 V CMOS level output swing. The input

protection circuitry on this device allows overvoltage tolerance on the input, allowing the device to be used as a logic–level translator from

3.0 V CMOS logic to 5.0 V CMOS Logic or from 1.8 V CMOS logic to 3.0 V CMOS Logic while operating at the high–voltage power

supply.

The L74VHC1GT14 input structure provides protection when voltages up to 7 V are applied, regardless of the supply voltage. This

allows the L74VHC1GT14 to be used to interface 5 V circuits to 3 V circuits. The output structures also provide protection when

V _CC= 0 V. These input and output structures help prevent device destruction caused by supply voltage – input/output voltage mismatch,

battery backup, hot insertion, etc. The LMC74VHC1GT14 can be used to enhance noise immunity or to square up slowly changing waveforms.

• Power Down Protection Provided on Inputs and Outputs

• Balanced Propagation Delays

• High Speed: t _PD= 4.5 ns (Typ) at V _CC= 5 V

• Low Power Dissipation: I _CC= 2 mA (Max) at T _A= 25°C

• TTL–Compatible Inputs: V _IL= 0.8 V; V _IH= 2.0 V

• Pin and Function Compatible with Other Standard Logic

Families

• CMOS–Compatible Outputs: V _OH> 0.8 V _CC

V _OL< 0.1 V _CC@ Load

;

• Chip Complexity: FETs = 100; Equivalent Gates = 25

MARKING DIAGRAMS

VC^d

SC–70/SC–88A/SOT–353

DF SUFFIX

Pin 1

d = Date Code

Figure 1. Pinout (Top View)

VC^d

Figure 2. Logic Symbol

SOT–23/TSOP–5/SC–59

DT SUFFIX

Pin 1

d = Date Code

PIN ASSIGNMENT

FUNCTION TABLE

IN A

Inputs

Output

GND

OUT Y

V _CC

ORDERING INFORMATION

See detailed ordering and shipping information in the

package dimensions section on page 5 of this data sheet.

1/6

12 3 4 5 6

中文翻译

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与L74VHC1GT14DFT1相关器件

型号	品牌	获取价格	描述	数据表
L74VHC1GT14DFT2	LRC	获取价格	Schmitt-Trigger Inverter/ CMOS Logic Level Shifter with LSTTL-Compatible Inputs
L74VHC1GT14DTT1	LRC	获取价格	Schmitt-Trigger Inverter/ CMOS Logic Level Shifter with LSTTL-Compatible Inputs
L74VHC1GT32	LRC	获取价格	2-Input OR Gate with LSTTL-Compatible Inputs
L74VHC1GT32DFT1	LRC	获取价格	2-Input OR Gate with LSTTL-Compatible Inputs
L74VHC1GT32DFT2	LRC	获取价格	2-Input OR Gate with LSTTL-Compatible Inputs
L74VHC1GT32DFT4	LRC	获取价格	2-Input OR Gate with LSTTL-Compatible Inputs
L74VHC1GT32DTT1	LRC	获取价格	2-Input OR Gate with LSTTL-Compatible Inputs
L74VHC1GT32DTT3	LRC	获取价格	2-Input OR Gate with LSTTL-Compatible Inputs
L74VHC1GT50	LRC	获取价格	Noninverting Buffer / CMOS Logic Level Shifter
L74VHC1GT50DFT1	LRC	获取价格	Noninverting Buffer / CMOS Logic Level Shifter

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