Datasheet > L74VHC1GT02DTT1

L74VHC1GT02DTT1

更新时间： 2022-12-23 07:20:45

品牌	Logo	应用领域
乐山 - LRC		转换器电平转换器栅
页数	文件大小	规格书
6页	200K
描述
2-Input NOR Gate / CMOS Logic Level Shifter with LSTTL-Compatible Inputs

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L74VHC1GT02DTT1 数据手册

LESHAN RADIO COMPANY, LTD.

2-Input NOR Gate / CMOS Logic Level Shifter

with LSTTL–Compatible Inputs

L74VHC1GT02

The L74VHC1GT02 is a single gate 2–input NOR fabricated with silicon gate CMOS technology. It achieves high speed operation

similar to equivalent Bipolar Schottky TTL while maintaining CMOS low power dissipation.

The internal circuit is composed of three stages, including a buffer output which provides high noise immunity and stable output.

The device input is compatible with TTL–type input thresholds and the output has a full 5.0 V CMOS level output swing. The input

protection circuitry on this device allows overvoltage tolerance on the input, allowing the device to be used as a logic–level translator from

3.0 V CMOS logic to 5.0 V CMOS Logic or from 1.8 V CMOS logic to 3.0 V CMOS Logic while operating at the high–voltage power

supply.

The L74VHC1GT02 input structure provides protection when voltages up to 7 V are applied, regardless of the supply voltage. This

allows the L74VHC1GT02 to be used to interface 5 V circuits to 3 V circuits. The output structures also provide protection when

V _CC= 0 V. These input and output structures help prevent device destruction caused by supply voltage – input/output voltage mismatch,

battery backup, hot insertion, etc.

• High Speed: tPD = 4.7 ns (Typ) at VCC = 5 V

• Low Power Dissipation: ICC = 2 mA (Max) at TA = 25°C

• TTL–Compatible Inputs: VIL = 0.8 V; VIH = 2.0 V

• CMOS–Compatible Outputs: VOH > 0.8 VCC ; VOL < 0.

1 VCC @Load

• Balanced Propagation Delays

• Pin and Function Compatible with Other Standard Logic Families

• Chip Complexity: FETs = 65; Equivalent Gates = 14

• Power Down Protection Provided on Inputs and Outputs

MARKING DIAGRAMS

VJ^d

SC–88A / SOT–353/SC–70

DF SUFFIX

Pin 1

d = Date Code

Figure 1. Pinout (Top View)

VJ^d

Figure 2. Logic Symbol

TSOP–5/SOT–23/SC–59

DT SUFFIX

Pin 1

d = Date Code

FUNCTION TABLE

PIN ASSIGNMENT

Inputs

Output

IN B

IN A

GND

OUT Y

V _CC

ORDERING INFORMATION

See detailed ordering and shipping information in the

package dimensions section on page 5 of this data sheet.

1/6

12 3 4 5 6

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