Datasheet > L6116CM15L

L6116CM15L

更新时间： 2024-11-12 20:31:19

品牌	Logo	应用领域
逻辑 - LOGIC		/
页数	文件大小	规格书
8页	163K
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数据手册

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L6116CM15L 数据手册

L6116

DEVICES INCORPORATED

2K x 8 Static RAM (Low Power)

L6116

2K x 8 Static RAM (Low Power)

DEVICES INCORPORATED

FEATURES

DESCRIPTION

q 2K x 8 Static RAM with Chip Select The L6116 is a high-performance, low- (typical) respectively, at 3 V, allowing

Powerdown, Output Enable

q Auto-Powerdown™Design

q Advanced CMOS Technology

q High Speed — to 15 ns maximum

q Low Power Operation

Active:

power CMOS Static RAM. The

storage circuitry is organized as 2048

words by 8 bits per word. The 8 Data

In and Data Out signals share I/O

pins. These devices are available in

three speeds with maximum access

times from 15 ns to 25 ns.

effective battery backup operation.

The L6116 provides asynchronous

(unclocked) operation with matching

access and cycle times. An active-low

Chip Enable and a three-state I/O bus

with a separate Output Enable control

simplify the connection of several

chips for increased storage capacity.

425 mW typical at 25 ns

Standby (typical):

400 µW (L6116)

Inputs and outputs are TTL compat-

ible. Operation is from a single +5 V

power supply. Power consumption

for the L6116 is 425 mW (typical) at

25 ns. Dissipation drops to 60 mW

(typical) for the L6116 and 50 mW

(typical) for the L6116-L when the

memory is deselected.

Memory locations are specified on

address pins A0 through A10. Reading

from a designated location is

200 µW (L6116-L)

q Data Retention at 2 V for Battery

Backup Operation

q DESC SMD No.

accomplished by presenting an

address and driving CE and OE LOW,

while WE remains HIGH. The data in

the addressed memory location will

then appear on the Data Out pins

within one access time. The output

pins stay in a high-impedance state

when CE or OE is HIGH, or WE is

LOW.

5962-84036 — L6116

5962-89690 — L6116

5962-88740 — L6116-L

Two standby modes are available.

Proprietary Auto-Powerdown™

circuitry reduces power consumption

automatically during read or write

accesses which are longer than the

minimum access time or when the

memory is deselected. In addition,

data may be retained in inactive

storage with a supply voltage as low

as 2 V. The L6116 and L6116-L

consume only 30 µW and 15 µW

q Available 100% Screened to

MIL-STD-883, Class B

q Plug Compatible with IDT6116,

Cypress CY7C128/CY6116

q Package Styles Available:

• 24-pin Plastic DIP

Writing to an addressed location is

accomplished when the active-low CE

and WE inputs are both LOW. Either

signal may be used to terminate the

write operation. Data In and Data Out

signals have the same polarity.

• 24-pin CerDIP

• 24-pin Plastic SOJ

• 24-pin Ceramic Flatpack

• 28-pin Ceramic LCC

• 32-pin Ceramic LCC

Latchup and static discharge pro-

tection are provided on-chip. The

L6116 can withstand an injection

current of up to 200 mA on any pin

without damage.

L6116 BLOCK DIAGRAM

128 x 16 x 8

MEMORY

ARRAY

ROW

ADDRESS

COLUMN SELECT

& COLUMN SENSE

I/O7-0

CONTROL

COLUMN ADDRESS

16K Static RAMs

03/21/95–LDS.6116-F

12 3 4 5 6 7 8

中文翻译

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与L6116CM15L相关器件

型号	品牌	获取价格	描述	数据表
L6116CM20	LOGIC	获取价格	Standard SRAM, 2KX8, 20ns, CMOS, CDIP24, 0.300 INCH, CERDIP-24
L6116CM20L	LOGIC	获取价格	Standard SRAM, 2KX8, 20ns, CMOS, CDIP24, 0.300 INCH, CERDIP-24
L6116CM25	LOGIC	获取价格	Standard SRAM, 2KX8, 25ns, CMOS, CDIP24, 0.300 INCH, CERDIP-24
L6116CM25L	LOGIC	获取价格	Standard SRAM, 2KX8, 25ns, CMOS, CDIP24, 0.300 INCH, CERDIP-24
L6116CM35	LOGIC	获取价格	Standard SRAM, 2KX8, 35ns, CMOS, CDIP24, 0.300 INCH, CERDIP-24
L6116CM45	ETC	获取价格	x8 SRAM
L6116CM85	ETC	获取价格	x8 SRAM
L6116CMB12	LOGIC	获取价格	Standard SRAM, 2KX8, 12ns, CMOS, CDIP24, 0.300 INCH, CERAMIC, DIP-24
L6116CMB12L	ETC	获取价格	x8 SRAM
L6116CMB15	ETC	获取价格	x8 SRAM

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