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L5991 PDF预览

L5991

更新时间: 2024-09-22 22:17:43
品牌 Logo 应用领域
意法半导体 - STMICROELECTRONICS 控制器
页数 文件大小 规格书
19页 194K
描述
PRIMARY CONTROLLER WITH STANDBY

L5991 技术参数

是否Rohs认证: 符合生命周期:Obsolete
零件包装代码:DIP包装说明:DIP, DIP16,.3
针数:16Reach Compliance Code:unknown
ECCN代码:EAR99HTS代码:8542.39.00.01
风险等级:5.71模拟集成电路 - 其他类型:SWITCHING CONTROLLER
控制模式:CURRENT-MODE控制技术:PULSE WIDTH MODULATION
最大输入电压:21 V最小输入电压:12 V
标称输入电压:15 VJESD-30 代码:R-PDIP-T16
JESD-609代码:e4功能数量:1
端子数量:16最大输出电流:1.5 A
标称输出电压:2.5 V封装主体材料:PLASTIC/EPOXY
封装代码:DIP封装等效代码:DIP16,.3
封装形状:RECTANGULAR封装形式:IN-LINE
峰值回流温度(摄氏度):NOT SPECIFIED认证状态:Not Qualified
座面最大高度:5.1 mm子类别:Switching Regulator or Controllers
最大供电电流 (Isup):13 mA表面贴装:NO
切换器配置:SINGLE最大切换频率:1000 kHz
技术:BCDMOS端子面层:Nickel/Palladium/Gold (Ni/Pd/Au)
端子形式:THROUGH-HOLE端子节距:2.54 mm
端子位置:DUAL处于峰值回流温度下的最长时间:NOT SPECIFIED
宽度:7.62 mmBase Number Matches:1

L5991 数据手册

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L5991  
L5991A  
PRIMARY CONTROLLER WITH STANDBY  
CURRENT-MODE CONTROL PWM  
SWITCHING FREQUENCY UP TO 1MHz  
MULTIPOWER BCD TECHNOLOGY  
LOW START-UP CURRENT (< 120 A)  
µ
HIGH-CURRENT OUTPUT DRIVE SUITABLE  
FOR POWER MOSFET (1A)  
FULLY LATCHED PWM LOGIC WITH DOU-  
BLE PULSE SUPPRESSION  
PROGRAMMABLE DUTY CYCLE  
100%AND 50%MAXIMUMDUTY CYCLELIMIT  
STANDBY FUNCTION  
DIP16  
SO16  
PROGRAMMABLE SOFT START  
PRIMARY OVERCURRENT FAULT DETEC-  
TION WITH RE-START DELAY  
PWM UVLO WITH HYSTERESIS  
IN/OUT SYNCHRONIZATION  
LATCHED DISABLE  
INTERNAL 100ns LEADING EDGE BLANK-  
ING OF CURRENT SENSE  
ORDERING NUMBERS:  
L5991/L5991A (DIP16)  
L5991D/L5991AD (SO16)  
line or DC-DC power supply applications using a  
fixed frequencycurrent mode control.  
Based on a standard current mode PWM control-  
ler this device includes some features such as  
programmable soft start, IN/OUT synchronization,  
disable (to be used for over voltage protection and  
for power management), precise maximum Duty  
Cycle Control, 100ns leading edge blanking on  
current sense, pulse by pulse current limit, over-  
current protection with soft start intervention, and  
Standbyfunction for oscillator frequencyreduction  
when the converteris lightly loaded.  
PACKAGE:DIP16 AND SO16  
DESCRIPTION  
This primary controller I.C., developed in BCD60II  
technology, has been designed to implement off  
BLOCK DIAGRAM  
VCC  
SYNC  
DC-LIM  
15  
VREF  
4
1
8
2
TIMING  
RCT  
25V  
Vref  
+
-
3
+
-
DC  
T
15V/10V  
PWM UVLO  
14  
9
-
DIS  
DIS  
VC  
+
2.5V  
13V  
10  
OUT  
BLANKING  
PWM  
S
Q
R
OVER CURRENT  
VREF  
VREF OK  
CLK  
DIS  
11  
16  
13  
PGND  
ST-BY  
FAULT  
SOFT-START  
ISEN  
SS  
+
-
STAND-BY  
2.5V  
1.2V  
7
+
E/A  
-
5
VFB  
2R  
1V  
R
12  
6
D97IN725A  
SGND  
COMP  
1/23  
August 1999  

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