L29C520/521
DEVICES INCORPORATED
4 x 8-bit Multilevel Pipeline Register
L29C520/521
4 x 8-bit Multilevel Pipeline Register
DEVICES INCORPORATED
FEATURES
DESCRIPTION
The L29C520 and L29C521 are pin-
for-pin compatible with the
IDT29FCT520/IDT29FCT521 and
AMD Am29520/Am29521, imple-
mented in low power CMOS.
The S1-0 select lines control a 4-to-1
multiplexer which routes the contents
of any of the registers to the Y output
pins. The independence of the I and S
controls allows simultaneous write
and read operations on different
registers.
❑ Four 8-bit Registers
❑ ImplementsDouble2-StagePipeline
or Single 4-Stage Pipeline Register
❑ Hold, Shift, and Load Instructions
❑ Separate Data In and Data Out Pins
The L29C520 and L29C521 contain
four registers which can be configured
as two independent, 2-level pipelines
or as one 4-level pipeline.
❑ High-Speed,LowPowerCMOS
Technology
❑ Three-State Outputs
TABLE 1.
L29C520 INSTRUCTION TABLE
❑ Replaces IDT29FCT520/IDT29FCT521
and AMD Am29520/Am29521
The Instruction pins, I1-0, control the
loading of the registers. For either
device, the registers may be config-
ured as a four-stage delay line, with
data loaded into R1 and shifted
sequentially through R2, R3, and R4.
Also, for the L29C520, data may be
loaded from the inputs into either R1
or R3 with only R2 or R4 shifting. The
L29C521 differs from the L29C520 in
that R2 and R4 remain unchanged
during this type of data load, as
shown in Tables 1 and 2. Finally, I1-0
may be set to prevent any register
from changing.
❑ Package Styles Available:
I1 I0 Description
• 24-pin PDIP
L
L
L
H
L
D➞R1 R1➞R2 R2➞R3 R3➞R4
• 28-pinPLCC, J-Lead
HOLD HOLD
D➞R3
R3➞R4
H
H
D➞R1 R1➞R2 HOLD
HOLD
H
ALL REGISTERS ON HOLD
TABLE 2.
L29C521 INSTRUCTION TABLE
I1 I0 Description
L
L
L
H
L
D➞R1 R1➞R2 R2➞R3 R3➞R4
HOLD HOLD
D➞R3
HOLD
HOLD
H
H
D➞R1 HOLD
HOLD
L29C520/521 BLOCK DIAGRAM
H
ALL REGISTERS ON HOLD
TABLE 3. OUTPUT SELECT
S1 S0 Register Selected
8
L
L
L
H
L
Register 4
Register 3
Register 2
Register 1
D8-0
REG 1
H
H
8
REG 2
Y
7-0
H
REG 3
REG 4
OE
2
S
1-0
2
I
1-0
CLK
Pipeline Registers
08/02/2000–LDS.520/1-P
1