Datasheet > L10C11

L10C11

更新时间： 2024-09-23 22:47:27

品牌	Logo	应用领域
逻辑 - LOGIC		移位寄存器
页数	文件大小	规格书
6页	68K
描述
4/8-bit Variable Length Shift Register

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L10C11 数据手册

L10C11

DEVICES INCORPORATED

4/8-bit Variable Length Shift Register

L10C11

4/8-bit Variable Length Shift Register

DEVICES INCORPORATED

FEATURES

DESCRIPTION

The L10C11 is a high-speed, low

R18’. Note that the minimum-length

path from data inputs to outputs is R1

to R2 to R18, consisting of three stages

of delay.

❑ Variable Length 4 or 8-bit Wide

Shift Register

power CMOS variable length shift

4-bit wide, adjustable length shift

registers. These registers share control

signals and a common clock. Both

shift registers can be programmed

together to any length from 3 to 18

stages inclusive, or one register can be

fixed at 18 stages of delay while the

other is variable. The configuration

implemented is determined by the

Length Code (L3-0) and the MODE

control line as shown in Table 1.

❑ Selectable Delay Length from 3 to

18 Stages

❑ Low Power CMOS Technology

❑ Replaces Fairchild TMC2011

❑ Load, Shift, and Hold Instructions

❑ Separate Data In and Data Out Pins

❑ Package Styles Available:

• 24-pin Plastic DIP

The MODE input determines whether

one or both of the internal shift

registers have variable length. When

MODE = 0, both D3-0 and D7-4 are

delayed by an amount which is

controlled by L3-0. When MODE = 1,

the D7-4 field is delayed by 18 stages

independent of L3-0.

• 28-pin Plastic LCC, J-Lead

The Length Code (L3-0) controls the

number of stages of delay applied to

the D inputs as shown in Table 1.

When the Length Code is 0, the inputs

are delayed by 3 clock periods. When

the Length Code is 1, the delay is 4

clock periods, and so forth. The

Length Code and MODE inputs are

latched on the rising edge of CLK.

Both the Length Code and MODE

values may be changed at any time

without affecting the contents of

registers R1 through R17 or R1’

through R17’.

Each input is applied to a chain of

registers which are clocked on the

rising edge of the common CLK input.

These registers are numbered R1

through R17 and R1’ through R17’,

corresponding to the D3-0 and D7-4

data fields respectively. A multi-

plexer serves to route the contents of

any of registers R2 through R17 to the

output register, denoted R18. A

similar multiplexer operates on the

contents of R2’ through R17’ to load

L10C11 BLOCK DIAGRAM

R17

R16

R15

D3-0

Y3-0

CLK

L3-0

MODE

R17’

R16’

R15’

D7-4

Y7-4

R4’

R3’

R2’

Pipeline Registers

03/27/2000–LDS.11-L

12 3 4 5 6

中文翻译

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与L10C11相关器件

型号	品牌	获取价格	描述	数据表
L10C11CC15	LOGIC	获取价格	Pipeline Register, 8-Bit, CMOS, CDIP24, 0.300 INCH, CERAMIC, DIP-24
L10C11CC20	LOGIC	获取价格	Pipeline Register, 8-Bit, CMOS, CDIP24, 0.300 INCH, CERAMIC, DIP-24
L10C11CC25	LOGIC	获取价格	Pipeline Register, 8-Bit, CMOS, CDIP24, 0.300 INCH, CERAMIC, DIP-24
L10C11CM20	LOGIC	获取价格	Pipeline Register, 8-Bit, CMOS, CDIP24, 0.300 INCH, CERAMIC, DIP-24
L10C11CM25	LOGIC	获取价格	Pipeline Register, 8-Bit, CMOS, CDIP24, 0.300 INCH, CERAMIC, DIP-24
L10C11CM30	LOGIC	获取价格	Pipeline Register, 8-Bit, CMOS, CDIP24, 0.300 INCH, CERAMIC, DIP-24
L10C11CMB20	LOGIC	获取价格	Pipeline Register, 8-Bit, CMOS, CDIP24, 0.300 INCH, CERAMIC, DIP-24
L10C11CMB25	LOGIC	获取价格	Pipeline Register, 8-Bit, CMOS, CDIP24, 0.300 INCH, CERAMIC, DIP-24
L10C11CMB30	LOGIC	获取价格	暂无描述
L10C11CME30	LOGIC	获取价格	Pipeline Register, 8-Bit, CMOS, CDIP24, 0.300 INCH, CERDIP-24

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