Datasheet > KM416V4104B

KM416V4104B

更新时间： 2024-09-25 22:36:23

品牌	Logo	应用领域
三星 - SAMSUNG		存储
页数	文件大小	规格书
36页	805K
描述
4M x 16bit CMOS Dynamic RAM with Extended Data Out

阅读下载

中文翻译

获取价格

数据手册

如果您发现信息不准确，欢迎纠错

KM416V4104B 数据手册

KM416V4004B,KM416V4104B

CMOS DRAM

4M x 16bit CMOS Dynamic RAM with Extended Data Out

DESCRIPTION

This is a family of 4,194,304 x 16 bit Extended Data Out Mode CMOS DRAMs. Extended Data Out Mode offers high speed random

access of memory cells within the same row. Refresh cycle(4K Ref. or 8K Ref.), access time (-45, -5 or -6), power consumption(Normal

or Low power) are optional features of this family. All of this family have CAS-before-RAS refresh, RAS-only refresh and Hidden refresh

capabilities. Furthermore, Self-refresh operation is available in L-version. This 4Mx16 EDO Mode DRAM family is fabricated using Sam-

sung¢s advanced CMOS process to realize high band-width, low power consumption and high reliability.

• Extended Data Out Mode operation

FEATURES

• 2 CAS Byte/Word Read/Write operation

• Part Identification

• CAS-before-RAS refresh capability

• RAS-only and Hidden refresh capability

• Fast parallel test mode capability

• Self-refresh capability (L-ver only)

• LVTTL(3.3V) compatible inputs and outputs

• Early Write or output enable controlled write

• JEDEC Standard pinout

- KM416V4004B/B-L(3.3V, 8K Ref.)

- KM416V4104B/B-L(3.3V, 4K Ref.)

• ActivePowerDissipation

Unit : mW

Speed

-45

-5

• Available in Plastic TSOP(II) packages

• +3.3V±0.3V power supply

360

324

288

468

432

-6

396

• Refresh Cycles

FUNCTIONAL BLOCK DIAGRAM

Part

NO.

Refresh

cycle

Refresh time

Normal

L-ver

RAS

UCAS

LCAS

Vcc

Vss

Control

KM416V4004B*

KM416V4104B

64ms

128ms

Clocks

VBB Generator

Lower

Data in

Buffer

* Access mode & RAS only refresh mode

: 8K cycle/64ms(Normal), 8K cycle/128ms(L-ver.)

CAS-before-RAS & Hidden refresh mode

DQ0

DQ7

Row Decoder

Refresh Timer

Lower

Data out

Buffer

Refresh Control

Memory Array

: 4K cycle/64ms(Normal), 4K cycle/128ms(L-ver.)

4,194,304 x 16

Cells

Refresh Counter

Row Address Buffer

Col. Address Buffer

Upper

Data in

Buffer

• Performance Range

DQ8

DQ15

Speed

tRAC

50ns

60ns

tCAC

12ns

13ns

15ns

tRC

tHPC

17ns

20ns

25ns

A0~A12

(A0~A11)*1

Upper

Data out

Buffer

-45

-5

74ns

84ns

104ns

A0~A8

(A0~A9)*1

Column Decoder

-6

Note) *1 : 4K Refresh

SAMSUNG ELECTRONICS CO., LTD. reserves the right to

change products and specifications without notice.

12 3 4 5 6 7...36

中文翻译

下载PDF

与KM416V4104B相关器件

型号	品牌	获取价格	描述	数据表
KM416V4104BS-5	SAMSUNG	获取价格	EDO DRAM, 4MX16, 50ns, CMOS, PDSO50, 0.400 INCH, PLASTIC, TSOP2-50
KM416V4104BS-5M	SAMSUNG	获取价格	EDO DRAM, 4MX16, 50ns, CMOS, PDSO50
KM416V4104BS-6	SAMSUNG	获取价格	EDO DRAM, 4MX16, 60ns, CMOS, PDSO50, 0.400 INCH, PLASTIC, TSOP2-50
KM416V4104BS-6TO	SAMSUNG	获取价格	EDO DRAM, 4MX16, 60ns, CMOS, PDSO50
KM416V4104BS-L45	SAMSUNG	获取价格	EDO DRAM, 4MX16, 45ns, CMOS, PDSO50, 0.400 INCH, PLASTIC, TSOP2-50
KM416V4104BS-L5TO	SAMSUNG	获取价格	EDO DRAM, 4MX16, 50ns, CMOS, PDSO50
KM416V4104BS-L6DE	SAMSUNG	获取价格	EDO DRAM, 4MX16, 60ns, CMOS, PDSO50
KM416V4104BS-L6K	SAMSUNG	获取价格	EDO DRAM, 4MX16, 60ns, CMOS, PDSO50
KM416V4104BS-L6T	SAMSUNG	获取价格	EDO DRAM, 4MX16, 60ns, CMOS, PDSO50
KM416V4104BS-L6TH	SAMSUNG	获取价格	EDO DRAM, 4MX16, 60ns, CMOS, PDSO50

与KM416V4104B相关文章

塔塔电子与力积电达成技术转让协议，携手建设印度首座晶圆厂
2024-09-29

9
英特尔震撼发布：128核心256线程的至强6性能核处理器
2024-09-29

8
SK海力士量产12层HBM3E，容量高达36GB
2024-09-27

12
意法半导体传感器驱动Sphere，开启沉浸式电影新时代
2024-09-27

19

产品中心

服务支持

精选活动

关于我们

帮助中心

KM416V4104B

KM416V4104B 数据手册

与KM416V4104B相关器件

与KM416V4104B相关文章

您还可以找

产品中心

服务支持

精选活动

关于我们

帮助中心

KM416V4104B

KM416V4104B 数据手册

与KM416V4104B相关器件

与KM416V4104B相关文章

您还可以找

您在本页遇到什么问题？