Datasheet > KKA8842

KKA8842

更新时间： 2024-02-08 00:16:36

品牌	Logo	应用领域
可天士 - KODENSHI		电视
页数	文件大小	规格书
15页	353K
描述
I2C BUS CONTROLLED SINGLE CHIP TV-RECEIVER

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中文翻译

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数据手册

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KKA8842 数据手册

TECHNICAL DATA

I²C BUS CONTROLLED SINGLE CHIP TV-RECEIVER

The KKA 8842 is I²C-bus controlled single chip TV processor which is intended to be applied in PAL,

NTSC, PAL/NTSC and multi-standard television receivers.

FEATURES

The following features are available:

•

Multi-standard vision IF circuit with an alignment-free PLL

demodulator without external components

Alignment-free multi-standard FM sound demodulator (4.5 MHz

to 6.5 MHz)

•

Audio switch

Automatic Volume Limiting

Flexible source selection with CVBS switch and Y(CVBS)/C input

so that a comb filter can be applied

•

Integrated chrominance trap circuit

Integrated luminance delay line

Asymmetrical peaking in the luminance channel with a

(defeatable) noise coring function

•

PAL/SECAM/NTSC decoder

Base-band delay line for PAL and SECAM or chroma comb filter

for NTSC

•

Black stretching of non-standard CVBS or luminance signals

Integrated chroma band-pass filter with switchable centre

frequency

•

Dynamic skin tone control circuit

Blue stretch circuit which offsets colours near white towards blue

RGB control circuit with "Continuous Cathode Calibration" and

white point adjustment

•

Possibility to insert a "blue back" option when no video signal is

available

Horizontal synchronization with two control loops and alignment-

free horizontal oscillator

•

Vertical count-down circuit

Vertical driver optimised for DC-coupled vertical output stages

I²C-bus control of various functions

12 3 4 5 6 7...15

中文翻译

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