KK4053BN

更新时间： 2024-09-17 03:48:07

品牌	Logo	应用领域
可天士 - KODENSHI		解复用器栅
页数	文件大小	规格书
7页	392K
描述
Analog Multiplexer Demultiplexer High-Performance Silicon-Gate CMOS

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KK4053BN 数据手册

TECHNICAL DATA

KK4053B

Analog Multiplexer Demultiplexer

High-Performance Silicon-Gate CMOS

The KK4053B analog multiplexer/demultiplexer is digitally controlled

analog switches having low ON impedance and very low OFF leakage

current. Control of analog signals up to 20V peak-to-peak can be

achieved by digital signal amplitudes of 4.5 to 20V (if V_CC- GND = 3V,

a V_CC- V_EEof up to 13 V can be controlled; for V_CC- V_EElevel

differences above 13V a V_CC- GND of at least 4.5V is required).

These multiplexer circuits dissipate extremely low quiescent power

over the full V_CC-GND and V_CC- V_EEsupply-voltage ranges,

independent of the logic state of the control signals. When a logic “1”is

present at the ENABLE input terminal all channels are off.

ORDERING INFORMATION

KK4053BN

KK4053BD

Plastic DIP

SOIC

T_A= -55° to 125° C for all packages

The KK4053B is a triple 2-channel multiplexer having three separate

digital control inputs, A, B, and C, and an enable input. Each control

input selects one of a pair of channels which are connected in a single-

pole double-throw configuration.

•

Operating Voltage Range: 3.0 to 18 V

Maximum input current of 1 µA at 18 V over full package-temperature

range; 100 nA at 18 V and 25°C

PIN ASSIGNMENT

•

Noise margin (over full package temperature range):

1.0 V min @ 5.0 V supply

2.0 V min @ 10.0 V supply

2.5 V min @ 15.0 V supply

LOGIC DIAGRAM

Triple Single-Pole, Double-Position

Plus Common Off

FUNCTION TABLE

Control Inputs

Enable

Select

Channels

PIN 16 =V_CC

PIN 7 = V_EE

PIN 8 = GND

None

H = high level

L = low level

X = don’t care

12 3 4 5 6 7

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