Datasheet > KAD5612P-21

KAD5612P-21

更新时间： 2024-11-26 14:57:19

品牌	Logo	应用领域
瑞萨 - RENESAS		/
页数	文件大小	规格书
29页	1505K
描述
12-Bit, 210MSPS Dual-Channel ADC with LVDS/LVCMOS Outputs

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KAD5612P-21 数据手册

DATASHEET

KAD5612P

Dual 12-Bit, 250/210/170/125MSPS A/D Converter

FN6803

Rev 3.00

May 26, 2016

The KAD5612P is a family of low-power, high-performance,

dual-channel 12-bit, analog-to-digital converters. Designed

with FemtoCharge™ technology on a standard CMOS process,

the family supports sampling rates of up to 250MSPS. The

KAD5612P-25 is the fastest member of this pin-compatible

family, which also features sample rates of 210MSPS

(KAD5612P-21), 170MSPS (KAD5612P-17) and 125MSPS

(KAD5612P-12).

Features

• Programmable gain, offset and skew control

• 1.3GHz analog input bandwidth

• 60fs clock jitter

• Over-range indicator

• Selectable clock divider: ÷1, ÷2 or ÷4

• Clock phase selection

A Serial Peripheral Interface (SPI) port allows for extensive

configurability, as well as fine control of gain, skew and offset

matching between the two converter cores.

• Nap and sleep modes

• Two’s complement, gray code or binary data format

• DDR LVDS-compatible or LVCMOS outputs

• Programmable built-in test patterns

• Single-supply 1.8V operation

• Pb-free (RoHS compliant)

Digital output data is presented in selectable LVDS or CMOS

formats. The KAD5612P is available in a 72 Ld QFN package

with an exposed paddle. Performance is specified over the full

industrial temperature range (-40°C to +85°C).

Key Specifications

Applications

• Power amplifier linearization

• SNR = 66.0dBFS for f = 105MHz (-1dBFS)

• SFDR = 86.0dBc for f = 105MHz (-1dBFS)

• Radar and satellite antenna array processing

• Broadband communications

• Power consumption

- 429mW at 250MSPS

- 342mW at 125MSPS

• High-performance data acquisition

• Communications test equipment

• WiMAX and microwave receivers

CLKP

CLKN

CLKOUTP

CLOCK

GENERATION

CLKOUTN

AINP

AINN

12-BIT

250MSPS

ADC

D[11:0]P

D[11:0]N

SHA

VREF

ORP

ORN

DIGITAL

ERROR

CORRECTION

VCM

OUTFMT

BINP

BINN

12-BIT

250MSPS

ADC

SHA

OUTMODE

VREF

1.25V

–

SPI

CONTROL

FIGURE 1. BLOCK DIAGRAM

FN6803 Rev 3.00

May 26, 2016

Page 1 of 29

12 3 4 5 6 7...29

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与KAD5612P-21相关器件

型号	品牌	获取价格	描述	数据表
KAD5612P-21Q72	INTERSIL	获取价格	Dual 12-Bit, 250/210/170/125MSPS A/D Converter
KAD5612P-25	INTERSIL	获取价格	Providing high-performance solutions for every link in the signal chain
KAD5612P-25	RENESAS	获取价格	12-Bit, 250MSPS Dual-Channel ADC with LVDS/LVCMOS Outputs
KAD5612P-25Q72	INTERSIL	获取价格	Dual 12-Bit, 250/210/170/125MSPS A/D Converter
KAD7000	SAMSUNG	获取价格	ADC, Dual-Slope, 1 Func, 1 Channel, 10 X 10 MM, QFP-48
KAD7000B	SAMSUNG	获取价格	ADC, Dual-Slope, 1 Func, 1 Channel, CMOS, PQFP48, 10 X 10 MM, QFP-48
KAD7001	SAMSUNG	获取价格	ADC, Proprietary Method, 1 Func, 1 Channel, PQFP80, 14 X 20 MM, QFP-80
KAD7001CQ	SAMSUNG	获取价格	ADC, Dual-Slope, 1 Func, 1 Channel, CMOS, PQFP80, 14 X 20 MM, QFP-80
KADG1-8080QB10Z1S	KINGBRIGHT	获取价格	SINGLE COLOR LED, BLUE, 6.4mm, ROHS COMPLIANT PACKAGE-2
KADG1-8080QB11Z1S/3	KINGBRIGHT	获取价格	SINGLE COLOR LED, BLUE, 6.4mm, ROHS COMPLIANT PACKAGE-2

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