Datasheet > KAD5612P-17

KAD5612P-17

更新时间： 2023-12-20 18:44:06

品牌	Logo	应用领域
瑞萨 - RENESAS		/
页数	文件大小	规格书
29页	1505K
描述
12-Bit, 170MSPS Dual-Channel ADC with LVDS/LVCMOS Outputs

阅读下载

获取价格

数据手册

如果您发现信息不准确，欢迎纠错

KAD5612P-17 数据手册

DATASHEET

KAD5612P

Dual 12-Bit, 250/210/170/125MSPS A/D Converter

FN6803

Rev 3.00

May 26, 2016

The KAD5612P is a family of low-power, high-performance,

dual-channel 12-bit, analog-to-digital converters. Designed

with FemtoCharge™ technology on a standard CMOS process,

the family supports sampling rates of up to 250MSPS. The

KAD5612P-25 is the fastest member of this pin-compatible

family, which also features sample rates of 210MSPS

(KAD5612P-21), 170MSPS (KAD5612P-17) and 125MSPS

(KAD5612P-12).

Features

• Programmable gain, offset and skew control

• 1.3GHz analog input bandwidth

• 60fs clock jitter

• Over-range indicator

• Selectable clock divider: ÷1, ÷2 or ÷4

• Clock phase selection

A Serial Peripheral Interface (SPI) port allows for extensive

configurability, as well as fine control of gain, skew and offset

matching between the two converter cores.

• Nap and sleep modes

• Two’s complement, gray code or binary data format

• DDR LVDS-compatible or LVCMOS outputs

• Programmable built-in test patterns

• Single-supply 1.8V operation

• Pb-free (RoHS compliant)

Digital output data is presented in selectable LVDS or CMOS

formats. The KAD5612P is available in a 72 Ld QFN package

with an exposed paddle. Performance is specified over the full

industrial temperature range (-40°C to +85°C).

Key Specifications

Applications

• Power amplifier linearization

• SNR = 66.0dBFS for f = 105MHz (-1dBFS)

• SFDR = 86.0dBc for f = 105MHz (-1dBFS)

• Radar and satellite antenna array processing

• Broadband communications

• Power consumption

- 429mW at 250MSPS

- 342mW at 125MSPS

• High-performance data acquisition

• Communications test equipment

• WiMAX and microwave receivers

CLKP

CLKN

CLKOUTP

CLOCK

GENERATION

CLKOUTN

AINP

AINN

12-BIT

250MSPS

ADC

D[11:0]P

D[11:0]N

SHA

VREF

ORP

ORN

DIGITAL

ERROR

CORRECTION

VCM

OUTFMT

BINP

BINN

12-BIT

250MSPS

ADC

SHA

OUTMODE

VREF

1.25V

–

SPI

CONTROL

FIGURE 1. BLOCK DIAGRAM

FN6803 Rev 3.00

May 26, 2016

Page 1 of 29

12 3 4 5 6 7...29

下载PDF

与KAD5612P-17相关器件

型号	品牌	描述	获取价格	数据表
KAD5612P-17Q72	INTERSIL	Dual 12-Bit, 250/210/170/125MSPS A/D Converter	获取价格
KAD5612P-21	INTERSIL	Providing high-performance solutions for every link in the signal chain	获取价格
KAD5612P-21	RENESAS	12-Bit, 210MSPS Dual-Channel ADC with LVDS/LVCMOS Outputs	获取价格
KAD5612P-21Q72	INTERSIL	Dual 12-Bit, 250/210/170/125MSPS A/D Converter	获取价格
KAD5612P-25	INTERSIL	Providing high-performance solutions for every link in the signal chain	获取价格
KAD5612P-25	RENESAS	12-Bit, 250MSPS Dual-Channel ADC with LVDS/LVCMOS Outputs	获取价格