Datasheet > KAD5610P-12

KAD5610P-12

更新时间： 2024-11-28 14:57:39

品牌	Logo	应用领域
瑞萨 - RENESAS		/
页数	文件大小	规格书
30页	1542K
描述
10-Bit, 125MSPS Dual-Channel ADC, with LVDS/LVCMOS Outputs

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KAD5610P-12 数据手册

DATASHEET

KAD5610P

Dual 10-Bit, 250/210/170/125MSPS A/D Converter

FN6810

Rev 3.00

May 31, 2016

The KAD5610P is a family of low-power, high performance,

dual-channel 10-bit, analog-to-digital converters. Designed

with Intersil’s proprietary FemtoCharge™ technology on a

standard CMOS process, the family supports sampling rates of

up to 250MSPS. The KAD5610P-25 is the fastest member of

this pin-compatible family, which also features sample rates of

210MSPS (KAD5610P-21), 170MSPS (KAD5610P-17) and

125MSPS (KAD5610P-12).

Features

• Programmable gain, offset and skew control

• 1.3GHz analog input bandwidth

• 60fs clock jitter

• Over-range indicator

• Selectable clock divider: ÷1, ÷2 or ÷4

• Clock phase selection

A Serial Peripheral Interface (SPI) port allows for extensive

configurability, as well as fine control of gain, skew and offset

matching between the two converter cores.

• Nap and sleep modes

• Two’s complement, gray code or binary data format

• DDR LVDS compatible or LVCMOS outputs

• Programmable built-in test patterns

• Single-supply 1.8V operation

• Pb-free (RoHs compliant)

Digital output data is presented in selectable LVDS or CMOS

formats. The KAD5610P is available in a 72 Ld QFN package

with an exposed paddle. Performance is specified over the full

industrial temperature range (-40°C to +85°C).

Key Specifications

Applications

• Power amplifier linearization

• SNR = 60.7dBFS for f = 105MHz (-1dBFS)

• SFDR = 86.1dBc for f = 105MHz (-1dBFS)

• Radar and satellite antenna array processing

• Broadband communications

• Power consumption

- 411mW at 250MSPS

- 327mW at 125MSPS

• High-performance data acquisition

• Communications test equipment

• WiMAX and microwave receivers

CLKP

CLKN

CLKOUTP

CLOCK

GENERATION

CLKOUTN

AINP

AINN

10-BIT

250MSPS

ADC

D[9:0]P

D[9:0]N

SHA

VREF

ORP

ORN

DIGITAL

ERROR

CORRECTION

VCM

OUTFMT

BINP

BINN

10-BIT

250MSPS

ADC

SHA

OUTMODE

VREF

1.25V

–

SPI

CONTROL

FIGURE 1. BLOCK DIAGRAM

FN6810 Rev 3.00

May 31, 2016

Page 1 of 30

12 3 4 5 6 7...30

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与KAD5610P-12相关器件

型号	品牌	获取价格	描述	数据表
KAD5610P-12Q72	INTERSIL	获取价格	Dual 10-Bit, 250/210/170/125MSPS A/D Converter
KAD5610P-17	INTERSIL	获取价格	Providing high-performance solutions for every link in the signal chain
KAD5610P-17	RENESAS	获取价格	10-Bit, 170MSPS Dual-Channel ADC, with LVDS/LVCMOS Outputs
KAD5610P-17Q72	INTERSIL	获取价格	Dual 10-Bit, 250/210/170/125MSPS A/D Converter
KAD5610P-21	INTERSIL	获取价格	Providing high-performance solutions for every link in the signal chain
KAD5610P-21	RENESAS	获取价格	10-Bit, 210MSPS Dual-Channel ADC, with LVDS/LVCMOS Outputs
KAD5610P-21Q72	INTERSIL	获取价格	Dual 10-Bit, 250/210/170/125MSPS A/D Converter
KAD5610P-25	INTERSIL	获取价格	Providing high-performance solutions for every link in the signal chain
KAD5610P-25	RENESAS	获取价格	10-Bit, 250MSPS Dual-Channel ADC, with LVDS/LVCMOS Outputs
KAD5610P-25Q72	INTERSIL	获取价格	Dual 10-Bit, 250/210/170/125MSPS A/D Converter

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