Datasheet > KAD5510P-50

KAD5510P-50

更新时间： 2024-11-22 14:57:19

品牌	Logo	应用领域
瑞萨 - RENESAS		/
页数	文件大小	规格书
30页	1526K
描述
10-Bit, 500MSPS Single-Channel ADC, with LVDS/LVCMOS Outputs

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KAD5510P-50 数据手册

DATASHEET

KAD5510P-50

10-Bit, 500MSPS A/D Converter

FN6811

Rev 3.00

May 31, 2016

The KAD5510P-50 is a low-power, high performance, 10-bit,

500MSPS analog-to-digital converter designed with Intersil’s

proprietary FemtoCharge™ technology on a standard CMOS

process. The KAD5510P-50 is part of a pin-compatible

portfolio of 10, 12 and 14-bit A/Ds with sample rates ranging

from 125MSPS to 500MSPS.

Features

• Programmable gain, offset and skew control

• 1.3GHz analog input bandwidth

• 60fs clock jitter

• Over-range indicator

The device utilizes two time-interleaved 10-bit, 250MSPS A/D

cores to achieve the ultimate sample rate of 500MSPS. A

single 500MHz conversion clock is presented to the converter,

and all interleave clocking is managed internally.

• Selectable clock divider: ÷1 or ÷2

• Clock phase selection

• Nap and sleep modes

A Serial Peripheral Interface (SPI) port allows for extensive

configurability, as well as fine control of matching

characteristics (gain, offset, skew) between the two converter

cores. These adjustments allow the user to minimize spurs

associated with the interleaving process.

• Two’s complement, gray code or binary data format

• DDR LVDS-compatible or LVCMOS outputs

• Programmable built-in test patterns

• Single-supply 1.8V operation

• Pb-free (RoHS compliant)

Digital output data is presented in selectable LVDS or CMOS

formats. The KAD5510P-50 is available in a 72 Ld QFN

package with an exposed paddle. Performance is specified

over the full industrial temperature range (-40°C to +85°C).

Applications

• Radar and satellite antenna array processing

• Broadband communications

Key Specifications

• High-performance data acquisition

• SNR = 60.7dBFS for f = 105MHz (-1dBFS)

• SFDR = 83.2dBc for f = 105MHz (-1dBFS)

• Power consumption = 414mW

CLKP

CLKN

CLOCK GENERATION

CLKOUTP

CLKOUTN

AND

INTERLEAVE CONTROL

10-BIT

250 MSPS

ADC

D[9:0]P

D[9:0]N

SHA

VREF

ORP

ORN

VINP

VINN

DIGITAL

ERROR

CORRECTION

OUTFMT

OUTMODE

10-BIT

250 MSPS

ADC

VCM

SHA

VREF

1.25V

–

SPI

CONTROL

FIGURE 1. BLOCK DIAGRAM

FN6811 Rev 3.00

May 31, 2016

Page 1 of 30

12 3 4 5 6 7...30

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与KAD5510P-50相关器件

型号	品牌	获取价格	描述	数据表
KAD5510P-50_09	INTERSIL	获取价格	10-Bit, 500MSPS A/D Converter
KAD5510P-50_0910	INTERSIL	获取价格	10-Bit, 500MSPS A/D Converter
KAD5510P-50Q72	INTERSIL	获取价格	10-Bit, 500MSPS A/D Converter
KAD5512HP	INTERSIL	获取价格	High Performance 12-Bit, 250/210/170/125MSPS ADC
KAD5512HP_09	INTERSIL	获取价格	High Performance 12-Bit, 250/210/170/125MSPS ADC
KAD5512HP_0910	INTERSIL	获取价格	High Performance 12-Bit, 250/210/170/125MSPS ADC
KAD5512HP-12	INTERSIL	获取价格	Providing high-performance solutions for every link in the signal chain
KAD5512HP-12	RENESAS	获取价格	12-Bit, 125MSPS Single-Channel ADC with LVDS/LVCMOS Outputs
KAD5512HP-12Q48	INTERSIL	获取价格	High Performance 12-Bit, 250/210/170/125MSPS ADC
KAD5512HP-12Q48	RENESAS	获取价格	12-Bit, 125MSPS Single-Channel ADC with LVDS/LVCMOS Outputs; QFN48, QFN72; Temp Range: -40

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