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K9F5616Q0B-HIB0 PDF预览

K9F5616Q0B-HIB0

更新时间： 2024-11-25 22:09:11
品牌 Logo 应用领域
三星 - SAMSUNG 闪存存储内存集成电路
页数 文件大小 规格书
34页 602K
描述
32M x 8 Bit , 16M x 16 Bit NAND Flash Memory

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中文翻译

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K9F5616Q0B-HIB0 技术参数

生命周期：Obsolete包装说明：FBGA, BGA63,10X12,32
Reach Compliance Code：compliant风险等级：5.84
Is Samacsys：N最长访问时间：30 ns
命令用户界面：YES数据轮询：NO
JESD-30 代码：R-PBGA-B63内存密度：268435456 bit
内存集成电路类型：FLASH内存宽度：16
部门数/规模：2K端子数量：63
字数：16777216 words字数代码：16000000
最高工作温度：85 °C最低工作温度：-40 °C
组织：16MX16封装主体材料：PLASTIC/EPOXY
封装代码：FBGA封装等效代码：BGA63,10X12,32
封装形状：RECTANGULAR封装形式：GRID ARRAY, FINE PITCH
页面大小：256 words并行/串行：PARALLEL
电源：1.8 V认证状态：Not Qualified
就绪/忙碌：YES部门规模：8K
最大待机电流：0.00005 A子类别：Flash Memories
最大压摆率：0.015 mA标称供电电压 (Vsup)：1.8 V
表面贴装：YES技术：CMOS
温度等级：INDUSTRIAL端子形式：BALL
端子节距：0.8 mm端子位置：BOTTOM
切换位：NO类型：NAND TYPE
Base Number Matches：1

K9F5616Q0B-HIB0 数据手册

 浏览型号K9F5616Q0B-HIB0的Datasheet PDF文件第2页浏览型号K9F5616Q0B-HIB0的Datasheet PDF文件第3页浏览型号K9F5616Q0B-HIB0的Datasheet PDF文件第4页浏览型号K9F5616Q0B-HIB0的Datasheet PDF文件第5页浏览型号K9F5616Q0B-HIB0的Datasheet PDF文件第6页浏览型号K9F5616Q0B-HIB0的Datasheet PDF文件第7页 
K9F5608U0B-VCB0,VIB0,FCB0,FIB0  
K9F5608Q0B-DCB0,DIB0,HCB0,HIB0  
K9F5608U0B-YCB0,YIB0,PCB0,PIB0  
K9F5608U0B-DCB0,DIB0,HCB0,HIB0  
K9F5616Q0B-DCB0,DIB0,HCB0,HIB0  
K9F5616U0B-YCB0,YIB0,PCB0,PIB0  
K9F5616U0B-DCB0,DIB0,HCB0,HIB0  
FLASH MEMORY  
Document Title  
32M x 8 Bit , 16M x 16 Bit NAND Flash Memory  
Revision History  
Revision No. History  
Draft Date  
Remark  
0.0  
Initial issue.  
May. 15th 2001  
Advance  
0.1  
At Read2 operation in X16 device  
Sep. 20th 2001  
: A3 ~ A7 are Don’t care ==> A3 ~ A7 are "L"  
0.2  
1. IOL(R/B) of 1.8V device is changed.  
Nov. 5th 2001  
-min. Value: 7mA -->3mA  
-typ. Value: 8mA -->4mA  
2. AC parameter is changed.  
tRP(min.) : 30ns --> 25ns  
3. WP pin provides hardware protection and is recommended to be kept  
at VIL during power-up and power-down and recovery time of minimum  
1ms is required before internal circuit gets ready for any command  
sequences as shown in Figure 15.  
---> WP pin provides hardware protection and is recommended to be  
kept at VIL during power-up and power-down and recovery time of  
minimum 10ms is required before internal circuit gets ready for any  
command sequences as shown in Figure 15.  
0.3  
0.4  
1. X16 TSOP1 pin is changed.  
: #36 pin is changed from VccQ to N.C .  
Feb. 15th 2002  
Apr. 15th 2002  
1. In X16 device, bad block information location is changed from 256th  
byte to 256th and 261th byte.  
2. tAR1, tAR2 are merged to tAR.(page 12)  
(before revision) min. tAR1 = 20ns , min. tAR2 = 50ns  
(after revision) min. tAR = 10ns  
3. min. tCLR is changed from 50ns to 10ns.(page12)  
4. min. tREA is changed from 35ns to 30ns.(page12)  
5. min. tWC is changed from 50ns to 45ns.(page12)  
6. Unique ID for Copyright Protection is available  
-The device includes one block sized OTP(One Time Programmable),  
which can be used to increase system security or to provide  
identification capabilities. Detailed information can be obtained by  
contact with Samsung.  
7. tRHZ is divide into tRHZ and tOH.(page 12)  
- tRHZ : RE High to Output Hi-Z  
- tOH : RE High to Output Hold  
8. tCHZ is divide into tCHZ and tOH.(page 12)  
- tCHZ : CE High to Output Hi-Z  
- tOH : CE High to Output Hold  
Note : For more detailed features and specifications including FAQ, please refer to Samsung’s Flash web site.  
http://www.intl.samsungsemi.com/Memory/Flash/datasheets.html  
The attached datasheets are prepared and approved by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserve the right  
to change the specifications. SAMSUNG Electronics will evaluate and reply to your requests and questions about device. If you have  
any questions, please contact the SAMSUNG branch office near you.  
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