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K4S51323LF-MC75 PDF预览

K4S51323LF-MC75

更新时间: 2024-09-17 19:32:31
品牌 Logo 应用领域
三星 - SAMSUNG 时钟动态存储器内存集成电路
页数 文件大小 规格书
12页 144K
描述
Synchronous DRAM, 16MX32, 5.4ns, CMOS, PBGA90

K4S51323LF-MC75 技术参数

是否Rohs认证: 不符合生命周期:Active
Reach Compliance Code:compliant风险等级:5.83
最长访问时间:5.4 ns最大时钟频率 (fCLK):133 MHz
I/O 类型:COMMON交错的突发长度:1,2,4,8
JESD-30 代码:R-PBGA-B90JESD-609代码:e0
内存密度:536870912 bit内存集成电路类型:SYNCHRONOUS DRAM
内存宽度:32端子数量:90
字数:16777216 words字数代码:16000000
最高工作温度:70 °C最低工作温度:-25 °C
组织:16MX32输出特性:3-STATE
封装主体材料:PLASTIC/EPOXY封装代码:FBGA
封装等效代码:BGA90,9X15,32封装形状:RECTANGULAR
封装形式:GRID ARRAY, FINE PITCH电源:2.5 V
认证状态:Not Qualified刷新周期:8192
连续突发长度:1,2,4,8,FP最大待机电流:0.001 A
子类别:DRAMs最大压摆率:0.3 mA
标称供电电压 (Vsup):2.5 V表面贴装:YES
技术:CMOS温度等级:OTHER
端子面层:Tin/Lead (Sn/Pb)端子形式:BALL
端子节距:0.8 mm端子位置:BOTTOM
Base Number Matches:1

K4S51323LF-MC75 数据手册

 浏览型号K4S51323LF-MC75的Datasheet PDF文件第2页浏览型号K4S51323LF-MC75的Datasheet PDF文件第3页浏览型号K4S51323LF-MC75的Datasheet PDF文件第4页浏览型号K4S51323LF-MC75的Datasheet PDF文件第5页浏览型号K4S51323LF-MC75的Datasheet PDF文件第6页浏览型号K4S51323LF-MC75的Datasheet PDF文件第7页 
K4S51323LF - M(E)C/L/F  
Mobile SDRAM  
4M x 32Bit x 4 Banks Mobile SDRAM in 90FBGA  
FEATURES  
GENERAL DESCRIPTION  
• VDD/VDDQ = 2.5V/2.5V or 2.5V/1.8V.  
• LVCMOS compatible with multiplexed address.  
• Four banks operation.  
The K4S51323LF is 536,870,912 bits synchronous high data  
rate Dynamic RAM organized as 4 x 4,196,304 words by 32 bits,  
fabricated with SAMSUNG’s high performance CMOS technol-  
ogy. Synchronous design allows precise cycle control with the  
use of system clock and I/O transactions are possible on every  
clock cycle. Range of operating frequencies, programmable  
burst lengths and programmable latencies allow the same  
device to be useful for a variety of high bandwidth and high per-  
formance memory system applications.  
• MRS cycle with address key programs.  
-. CAS latency (1, 2 & 3).  
-. Burst length (1, 2, 4, 8 & Full page).  
-. Burst type (Sequential & Interleave).  
• EMRS cycle with address key programs.  
• All inputs are sampled at the positive going edge of the system  
clock.  
• Burst read single-bit write operation.  
• Special Function Support.  
-. PASR (Partial Array Self Refresh).  
-. Internal TCSR (Temperature Compensated Self Refresh)  
• DQM for masking.  
• Auto refresh.  
• 64ms refresh period (8K cycle).  
• Commercial Temperature Operation (-25°C ~ 70°C).  
• 2Chips DDP 90Balls FBGA ( -MXXX -Pb, -EXXX -Pb Free).  
ORDERING INFORMATION  
Part No.  
Max Freq.  
133MHz(CL=3), 111MHz(CL=2)  
111MHz(CL=2)  
Interface  
Package  
K4S51323LF-M(E)C/L/F75  
K4S51323LF-M(E)C/L/F1H  
K4S51323LF-M(E)C/L/F1L  
90 FBGA Pb  
(Pb Free)  
LVCMOS  
111MHz(CL=3)*1, 83MHz(CL2)  
- M(E)C/L/F : Normal / Low / Low Power, Commercial Temperature(-25°C ~ 70°C)  
NOTES :  
1. In case of 40MHz Frequency, CL1 can be supported.  
2. Samsung shall not offer for sale or sell either directly or through and third-party proxy, and DRAM memory products that include "Multi-Die Plastic  
DRAM" for use as components in general and scientific computers such as, by way of example, mainframes, servers, work stations or desk top  
computers for the first three years of five year term of this license. Nothing herein limits the rights of Samsung to use Multi-Die Plastic DRAM in other  
products or other applications under paragrangh such as mobile, telecom or non-computer application(which include by way of example laptop or  
notebook computers, cell phones, televisions or visual monitors)  
Violation may subject the customer to legal claims and also excludes any warranty against infringement from Samsung." .  
3. Samsung are not designed or manufactured for use in a device or system that is used under circumstance in which human life is potentially at stake.  
Please contact to the memory marketing team in samsung electronics when considering the use of a product contained herein for any specific pur  
pose, such as medical, aerospace, nuclear, military, vehicular or undersea repeater use.  
1
September 2004  

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