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K4Q160411C-BC600 PDF预览

K4Q160411C-BC600

更新时间: 2024-11-19 21:18:07
品牌 Logo 应用领域
三星 - SAMSUNG 动态存储器光电二极管内存集成电路
页数 文件大小 规格书
20页 401K
描述
EDO DRAM, 4MX4, 60ns, CMOS, PDSO28, 0.300 INCH, PLASTIC, SOJ-28

K4Q160411C-BC600 技术参数

生命周期:Obsolete零件包装代码:SOJ
包装说明:SOJ,针数:28
Reach Compliance Code:unknownECCN代码:EAR99
HTS代码:8542.32.00.02风险等级:5.84
访问模式:FAST PAGE WITH EDO最长访问时间:60 ns
其他特性:RAS ONLY/CAS BEFORE RAS/HIDDEN REFRESHJESD-30 代码:R-PDSO-J28
长度:18.42 mm内存密度:16777216 bit
内存集成电路类型:EDO DRAM内存宽度:4
功能数量:1端口数量:1
端子数量:28字数:4194304 words
字数代码:4000000工作模式:ASYNCHRONOUS
最高工作温度:70 °C最低工作温度:
组织:4MX4封装主体材料:PLASTIC/EPOXY
封装代码:SOJ封装形状:RECTANGULAR
封装形式:SMALL OUTLINE认证状态:Not Qualified
座面最大高度:3.76 mm最大供电电压 (Vsup):5.5 V
最小供电电压 (Vsup):4.5 V标称供电电压 (Vsup):5 V
表面贴装:YES技术:CMOS
温度等级:COMMERCIAL端子形式:J BEND
端子节距:1.27 mm端子位置:DUAL
宽度:7.62 mmBase Number Matches:1

K4Q160411C-BC600 数据手册

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K4Q170411C, K4Q160411C  
CMOS DRAM  
4M x 4Bit CMOS Quad CAS DRAM with Extended Data Out  
DESCRIPTION  
This is a family of 4,194,304 x 4 bit Quad CAS with Extended Data Out Mode CMOS DRAMs. Extended Data Out Mode offers high  
speed random access of memory cells within the same row, so called Hyper Page Mode. Refresh cycle (2K Ref. or 4K Ref.), access  
time (-50 or -60), power consumption(Normal or Low power) and package type(SOJ or TSOP-II) are optional features of this family. All of  
this family have CAS-before-RAS refresh, RAS-only refresh and Hidden refresh capabilities. Furthermore, Self-refresh operation is avail-  
able in L-version. Four separate CAS pins provide for seperate I/O operation allowing this device to operate in parity mode.  
This 4Mx4 Extended Data Out Quad CAS DRAM family is fabricated using Samsung¢s advanced CMOS process to realize high band-  
width, low power consumption and high reliability.  
FEATURES  
• Extended Data Out mode operation  
(Fast Page Mode with Extended Data Out)  
Part Identification  
• Four separate CAS pins provide for separate I/O operation  
- K4Q170411C-B(F) (5V, 4K Ref.)  
- K4Q160411C-B(F) (5V, 2K Ref.)  
• CAS-before-RAS refresh capability  
• RAS-only and Hidden refresh capability  
• Self-refresh capability (L-ver only)  
• Fast parallel test mode capability  
• TTL compatible inputs and outputs  
• Early Write or output enable controlled write  
• JEDEC Standard pinout  
Active Power Dissipation  
Unit : mW  
Refresh Cycle  
Speed  
4K  
2K  
• Available in Plastic SOJ and TSOP(II) packages  
• Single +5V±10% power supply  
-50  
-60  
495  
440  
605  
550  
FUNCTIONAL BLOCK DIAGRAM  
Refresh Cycles  
Part  
NO.  
Refresh  
cycle  
Refresh period  
RAS  
CAS0 - 3  
W
Vcc  
Vss  
Control  
Clocks  
Normal  
L-ver  
VBB Generator  
K4Q170411C  
K4Q160411C  
4K  
2K  
64ms  
32ms  
128ms  
Data in  
Buffer  
Row Decoder  
Refresh Timer  
Refresh Control  
DQ0  
to  
DQ3  
Memory Array  
4,194,304 x 4  
Cells  
Refresh Counter  
Row Address Buffer  
Col. Address Buffer  
Performance Range  
Speed  
-50  
tRAC  
50ns  
60ns  
tCAC  
13ns  
15ns  
tRC  
tHPC  
20ns  
25ns  
A0-A11  
(A0 - A10)*1  
A0 - A9  
84ns  
Data out  
Buffer  
Column Decoder  
OE  
(A0 - A10)*1  
-60  
104ns  
Note) *1 : 2K Refresh  
SAMSUNG ELECTRONICS CO., LTD. reserves the right to  
change products and specifications without notice.  

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