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K4P160411C-B PDF预览

K4P160411C-B

更新时间: 2024-11-19 21:04:07
品牌 Logo 应用领域
三星 - SAMSUNG 动态存储器
页数 文件大小 规格书
20页 396K
描述
DRAM

K4P160411C-B 技术参数

生命周期:Active包装说明:,
Reach Compliance Code:compliant风险等级:5.75
Base Number Matches:1

K4P160411C-B 数据手册

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K4P170411C, K4P160411C  
CMOS DRAM  
4M x 4Bit CMOS Quad CAS DRAM with Fast Page Mode  
DESCRIPTION  
This is a family of 4,194,304 x 4 bit Quad CAS with Fast Page Mode CMOS DRAMs. Fast Page Mode offers high speed random access  
of memory cells within the same row. Refresh cycle (2K Ref. or 4K Ref.), access time (-50 or -60), power consumption(Normal or Low  
power) and package type(SOJ or TSOP-II) are optional features of this family. All of this family have CAS-before-RAS refresh, RAS-only  
refresh and Hidden refresh capabilities. Furthermore, Self-refresh operation is available in L-version. Four separate CAS pins provide for  
seperate I/O operation allowing this device to operate in parity mode.  
This 4Mx4 Fast Page Mode Quad CAS DRAM family is fabricated using Samsung¢s advanced CMOS process to realize high band-  
width, low power consumption and high reliability.  
FEATURES  
• Fast Page Mode operation  
• Four seperate CAS pins provide for separate I/O operation  
Part Identification  
• CAS-before-RAS refresh capability  
• RAS-only and Hidden refresh capability  
• Self-refresh capability (L-ver only)  
• Fast paralleltest mode capability  
- K4P170411C-B(F) (5V, 4K Ref.)  
- K4P160411C-B(F) (5V, 2K Ref.)  
• TTL compatible inputs and outputs  
• Early Write or output enable controlled write  
• JEDEC Standard pinout  
Active Power Dissipation  
Unit : mW  
Refresh Cycle  
Speed  
4K  
2K  
• Available in Plastic SOJ and TSOP(II) packages  
• Single +5V±10% power supply  
-50  
-60  
495  
440  
605  
550  
FUNCTIONAL BLOCK DIAGRAM  
Refresh Cycles  
Part  
NO.  
Refresh  
cycle  
Refresh period  
RAS  
CAS0 - 3  
W
Vcc  
Vss  
Control  
Clocks  
Normal  
L-ver  
VBB Generator  
K4P170411C  
K4P160411C  
4K  
2K  
64ms  
32ms  
128ms  
Data in  
Buffer  
Row Decoder  
Refresh Timer  
Refresh Control  
DQ0  
to  
DQ3  
Memory Array  
4,194,304 x 4  
Cells  
Performance Range  
Refresh Counter  
Row Address Buffer  
Col. Address Buffer  
Speed  
-50  
Remark  
tRAC  
50ns  
60ns  
tCAC  
tRC  
90ns  
tPC  
A0-A11  
(A0 - A10)*1  
A0 - A9  
13ns  
35ns 5V/3.3V  
Data out  
Buffer  
Column Decoder  
-60  
15ns 110ns 40ns 5V/3.3V  
OE  
(A0 - A10)*1  
Note) *1 : 2K Refresh  
SAMSUNG ELECTRONICS CO., LTD. reserves the right to  
change products and specifications without notice.  

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