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K4E160411D-F5000 PDF预览

K4E160411D-F5000

更新时间: 2024-11-20 14:16:55
品牌 Logo 应用领域
三星 - SAMSUNG 动态存储器光电二极管内存集成电路
页数 文件大小 规格书
21页 256K
描述
EDO DRAM, 4MX4, 50ns, CMOS, PDSO24, TSOP2-26/24

K4E160411D-F5000 技术参数

生命周期:Active包装说明:TSOP2,
Reach Compliance Code:compliantECCN代码:EAR99
风险等级:5.73Is Samacsys:N
访问模式:FAST PAGE WITH EDO最长访问时间:50 ns
其他特性:RAS ONLY/CAS BEFORE RAS/HIDDEN REFRESHJESD-30 代码:R-PDSO-G24
长度:17.14 mm内存密度:16777216 bit
内存集成电路类型:EDO DRAM内存宽度:4
功能数量:1端口数量:1
端子数量:24字数:4194304 words
字数代码:4000000工作模式:ASYNCHRONOUS
最高工作温度:70 °C最低工作温度:
组织:4MX4封装主体材料:PLASTIC/EPOXY
封装代码:TSOP2封装形状:RECTANGULAR
封装形式:SMALL OUTLINE, THIN PROFILE座面最大高度:1.2 mm
最大供电电压 (Vsup):5.5 V最小供电电压 (Vsup):4.5 V
标称供电电压 (Vsup):5 V表面贴装:YES
技术:CMOS温度等级:COMMERCIAL
端子形式:GULL WING端子节距:1.27 mm
端子位置:DUAL宽度:7.62 mm
Base Number Matches:1

K4E160411D-F5000 数据手册

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K4E170411D, K4E160411D  
K4E170412D, K4E160412D  
CMOS DRAM  
4M x 4Bit CMOS Dynamic RAM with Extended Data Out  
DESCRIPTION  
This is a family of 4.194,304 x 4 bit Extended Data Out CMOS DRAMs. Extended Data Out Mode offers high speed random access of  
memory cells within the same row, so called Hyper Page Mode. Power supply voltage (+5.0V or +3.3V), refresh cycle (2K Ref. or 4K  
Ref.), access time (-50 or -60), power consumption(Normal or Low power) and package type(SOJ or TSOP-II) are optional features of  
this family. All of this family have CAS-before-RAS refresh, RAS-only refresh and Hidden refresh capabilities. Furthermore, Self-refresh  
operation is available in L-version. This 4Mx4 EDO DRAM family is fabricated using Samsung¢s advanced CMOS process to realize high  
band-width, low power consumption and high reliability. It may be used as main memory unit for high level computer, microcomputer and  
personal computer.  
FEATURES  
Part Identification  
• Extended Data Out Mode operation  
(Fast Page Mode with Extended Data Out)  
• CAS-before-RAS refresh capability  
- K4E170411D-B(F) (5V, 4K Ref.)  
• RAS-only and Hidden refresh capability  
- K4E160411D-B(F) (5V, 2K Ref.)  
• Self-refresh capability (L-ver only)  
- K4E170412D-B(F) (3.3V, 4K Ref.)  
- K4E160412D-B(F) (3.3V, 2K Ref.)  
• Fast parallel test mode capability  
• TTL(5V)/LVTTL(3.3V) compatible inputs and outputs  
• Early Write or output enable controlled write  
• JEDEC Standard pinout  
ActivePowerDissipation  
Unit : mW  
5V  
• Available in Plastic SOJ and TSOP(II) packages  
• Single +5V±10% power supply (5V product)  
• Single +3.3V±0.3V power supply (3.3V product)  
3.3V  
Speed  
4K  
324  
288  
2K  
4K  
2K  
-50  
-60  
396  
360  
495  
440  
605  
550  
FUNCTIONAL BLOCK DIAGRAM  
Refresh Cycles  
Part  
Refresh Refresh period  
RAS  
CAS  
W
Vcc  
Vss  
VCC  
Control  
Clocks  
NO.  
cycle  
Normal L-ver  
VBB Generator  
K4E170411D  
5V  
4K  
64ms  
128ms  
32ms  
Data in  
K4E170412D 3.3V  
K4E160411D 5V  
Buffer  
Row Decoder  
Refresh Timer  
Refresh Control  
Refresh Counter  
2K  
K4E160412D 3.3V  
DQ0  
to  
DQ3  
Memory Array  
4,194,304 x4  
Cells  
Performance Range  
A0-A11  
(A0 - A10)*1  
A0 - A9  
Row Address Buffer  
Col. Address Buffer  
Speed  
-50  
Remark  
20ns 5V/3.3V  
tRAC  
50ns  
60ns  
tCAC  
15ns  
tRC  
tHPC  
Data out  
Buffer  
Column Decoder  
OE  
(A0 - A10)*1  
84ns  
-60  
17ns 104ns 25ns 5V/3.3V  
Note) *1 : 2K Refresh  
SAMSUNG ELECTRONICS CO., LTD. reserves the right to  
change products and specifications without notice.  

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EDO DRAM, 4MX4, 50ns, CMOS, PDSO24, 0.300 INCH, PLASTIC, TSOP2-26/24
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4M x 4Bit CMOS Dynamic RAM with Extended Data Out
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EDO DRAM, 4MX4, 50ns, CMOS, PDSO24, SOJ-26/24