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JM38510/65307BEA PDF预览

JM38510/65307BEA

更新时间: 2024-11-21 11:07:07
品牌 Logo 应用领域
德州仪器 - TI 逻辑集成电路触发器锁存器
页数 文件大小 规格书
22页 1176K
描述
具有清零端的六路 D 型触发器 | J | 16 | -55 to 125

JM38510/65307BEA 技术参数

生命周期:Active零件包装代码:DIP
包装说明:DIP,针数:16
Reach Compliance Code:not_compliantHTS代码:8542.39.00.01
风险等级:1.17系列:HC/UH
JESD-30 代码:R-GDIP-T16长度:19.56 mm
负载电容(CL):50 pF逻辑集成电路类型:D FLIP-FLOP
最大频率@ Nom-Sup:21000000 Hz最大I(ol):0.0052 A
位数:6功能数量:1
端子数量:16最高工作温度:125 °C
最低工作温度:-55 °C输出极性:TRUE
封装主体材料:CERAMIC, GLASS-SEALED封装代码:DIP
封装形状:RECTANGULAR封装形式:IN-LINE
包装方法:TUBE峰值回流温度(摄氏度):NOT SPECIFIED
最大电源电流(ICC):0.08 mAProp。Delay @ Nom-Sup:48 ns
传播延迟(tpd):240 ns认证状态:Not Qualified
筛选级别:MIL-M-38510 Class B座面最大高度:5.08 mm
最大供电电压 (Vsup):6 V最小供电电压 (Vsup):2 V
标称供电电压 (Vsup):5 V表面贴装:NO
技术:CMOS温度等级:MILITARY
端子形式:THROUGH-HOLE端子节距:2.54 mm
端子位置:DUAL处于峰值回流温度下的最长时间:NOT SPECIFIED
触发器类型:POSITIVE EDGE宽度:6.92 mm
最小 fmax:25 MHzBase Number Matches:1

JM38510/65307BEA 数据手册

 浏览型号JM38510/65307BEA的Datasheet PDF文件第2页浏览型号JM38510/65307BEA的Datasheet PDF文件第3页浏览型号JM38510/65307BEA的Datasheet PDF文件第4页浏览型号JM38510/65307BEA的Datasheet PDF文件第5页浏览型号JM38510/65307BEA的Datasheet PDF文件第6页浏览型号JM38510/65307BEA的Datasheet PDF文件第7页 
ꢀꢁꢂ ꢃ ꢄꢅ ꢆ ꢇꢃ ꢈ ꢀꢁꢇ ꢃꢄ ꢅꢆ ꢇꢃ  
ꢄꢉ ꢊ ꢋꢌꢍ ꢎꢏ ꢉ ꢐ ꢑ ꢒꢏ ꢌ ꢐꢑꢓ ꢏ ꢀ  
ꢔ ꢒꢍꢄ ꢅ ꢑꢉ ꢕꢖ  
SCLS119D − DECEMBER 1982 − REVISED SEPTEMBER 2003  
SN54HC174 . . . J OR W PACKAGE  
SN74HC174 . . . D, DB, N, NS, OR PW PACKAGE  
(TOP VIEW)  
D
D
D
D
D
D
D
Wide Operating Voltage Range of 2 V to 6 V  
Outputs Can Drive Up To 10 LSTTL Loads  
Low Power Consumption, 80-µA Max I  
CC  
CLR  
1Q  
V
CC  
1
2
3
4
5
6
7
8
16  
Typical t = 14 ns  
pd  
4-mA Output Drive at 5 V  
15 6Q  
14 6D  
13 5D  
12 5Q  
1D  
2D  
2Q  
Low Input Current of 1 µA Max  
Contain Six Flip-Flops With Single-Rail  
Outputs  
11  
10  
9
3D  
3Q  
GND  
4D  
4Q  
CLK  
D
Applications Include:  
− Buffer/Storage Registers  
− Shift Registers  
− Pattern Generators  
SN54HC174 . . . FK PACKAGE  
(TOP VIEW)  
description/ordering information  
These positive-edge-triggered D-type flip-flops  
have a direct clear (CLR) input.  
3
2
1
20 19  
18  
1D  
2D  
NC  
2Q  
3D  
6D  
5D  
4
5
6
7
8
Information at the data (D) inputs meeting the  
setup time requirements is transferred to the  
outputs on the positive-going edge of the clock  
(CLK) pulse. Clock triggering occurs at a  
particular voltage level and is not directly related  
to the transition time of the positive-going edge of  
CLK. When CLK is at either the high or low level,  
the D input has no effect at the output.  
17  
16 NC  
15  
14  
5Q  
4D  
9 10 11 12 13  
NC − No internal connection  
ORDERING INFORMATION  
ORDERABLE  
PART NUMBER  
TOP-SIDE  
MARKING  
T
A
PACKAGE  
PDIP − N  
PACKAGE  
Tube of 25  
Tube of 40  
SN74HC174N  
SN74HC174N  
SN74HC174D  
Reel of 2500  
Reel of 250  
Reel of 2000  
Reel of 2000  
Tube of 90  
SN74HC174DR  
SN74HC174DT  
SN74HC174NSR  
SN74HC174DBR  
SN74HC174PW  
SN74HC174PWR  
SN74HC174PWT  
SNJ54HC174J  
SOIC − D  
HC174  
SOP − NS  
HC174  
HC174  
−40°C to 85°C  
SSOP − DB  
Reel of 2000  
Reel of 250  
Tube of 25  
TSSOP − PW  
HC174  
CDIP − J  
CFP − W  
LCCC − FK  
SNJ54HC174J  
SNJ54HC174W  
SNJ54HC174FK  
Tube of 150  
Tube of 55  
SNJ54HC174W  
SNJ54HC174FK  
−55°C to 125°C  
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are  
available at www.ti.com/sc/package.  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
Copyright 2003, Texas Instruments Incorporated  
ꢓ ꢙ ꢤ ꢜ ꢛꢧ ꢢꢡ ꢟꢠ ꢡꢛ ꢝꢤ ꢦꢘ ꢞꢙ ꢟ ꢟꢛ ꢮꢒ ꢑꢌ ꢏꢖ ꢐ ꢌꢯꢰꢂ ꢯꢂꢈ ꢞꢦꢦ ꢤꢞ ꢜ ꢞ ꢝꢣ ꢟꢣꢜ ꢠ ꢞ ꢜ ꢣ ꢟꢣ ꢠꢟꢣ ꢧ  
ꢟ ꢣ ꢠ ꢟꢘ ꢙꢭ ꢛꢚ ꢞ ꢦꢦ ꢤꢞ ꢜ ꢞ ꢝ ꢣ ꢟ ꢣ ꢜ ꢠ ꢨ  
ꢢ ꢙꢦ ꢣꢠꢠ ꢛ ꢟꢩꢣ ꢜ ꢫꢘ ꢠꢣ ꢙ ꢛꢟꢣ ꢧꢨ ꢓ ꢙ ꢞꢦ ꢦ ꢛ ꢟꢩꢣ ꢜ ꢤꢜ ꢛ ꢧꢢꢡ ꢟꢠ ꢈ ꢤꢜ ꢛ ꢧꢢꢡ ꢟꢘꢛ ꢙ  
1
POST OFFICE BOX 655303 DALLAS, TEXAS 75265  

JM38510/65307BEA 替代型号

型号 品牌 替代类型 描述 数据表
8407301EA TI

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