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JM38510/37401B2A PDF预览

JM38510/37401B2A

更新时间: 2024-11-08 22:41:07
品牌 Logo 应用领域
德州仪器 - TI 栅极触发器逻辑集成电路输入元件
页数 文件大小 规格书
14页 495K
描述
QUADRUPLE 2-INPUT POSITIVE-AND GATES

JM38510/37401B2A 技术参数

生命周期:Active零件包装代码:QLCC
包装说明:LCC-20针数:20
Reach Compliance Code:not_compliantHTS代码:8542.39.00.01
Factory Lead Time:6 weeks风险等级:5.23
Is Samacsys:N系列:ALS
JESD-30 代码:S-CQCC-N20长度:8.89 mm
负载电容(CL):50 pF逻辑集成电路类型:AND GATE
最大I(ol):0.008 A功能数量:4
输入次数:2端子数量:20
最高工作温度:125 °C最低工作温度:-55 °C
封装主体材料:CERAMIC, METAL-SEALED COFIRED封装代码:QCCN
封装形状:SQUARE封装形式:CHIP CARRIER
包装方法:TUBE峰值回流温度(摄氏度):NOT SPECIFIED
最大电源电流(ICC):4 mAProp。Delay @ Nom-Sup:14 ns
传播延迟(tpd):14 ns认证状态:Not Qualified
施密特触发器:NO筛选级别:MIL-M-38510 Class B
座面最大高度:2.03 mm最大供电电压 (Vsup):5.5 V
最小供电电压 (Vsup):4.5 V标称供电电压 (Vsup):5 V
表面贴装:YES技术:TTL
温度等级:MILITARY端子形式:NO LEAD
端子节距:1.27 mm端子位置:QUAD
处于峰值回流温度下的最长时间:NOT SPECIFIED宽度:8.89 mm
Base Number Matches:1

JM38510/37401B2A 数据手册

 浏览型号JM38510/37401B2A的Datasheet PDF文件第2页浏览型号JM38510/37401B2A的Datasheet PDF文件第3页浏览型号JM38510/37401B2A的Datasheet PDF文件第4页浏览型号JM38510/37401B2A的Datasheet PDF文件第5页浏览型号JM38510/37401B2A的Datasheet PDF文件第6页浏览型号JM38510/37401B2A的Datasheet PDF文件第7页 
SN54ALS08, SN54AS08, SN74ALS08, SN74AS08  
QUADRUPLE 2-INPUT POSITIVE-AND GATES  
SDAS191A – APRIL 1982 – REVISED DECEMBER 1994  
SN54ALS08, SN54AS08 . . . J PACKAGE  
SN74ALS08, SN74AS08 . . . D OR N PACKAGE  
(TOP VIEW)  
Package Options Include Plastic  
Small-Outline (D) Packages, Ceramic Chip  
Carriers (FK), and Standard Plastic (N) and  
Ceramic (J) 300-mil DIPs  
1A  
1B  
V
CC  
1
2
3
4
5
6
7
14  
13  
12  
11  
10  
9
4B  
4A  
4Y  
3B  
3A  
3Y  
description  
1Y  
2A  
These devices contain four independent 2-input  
positive-AND gates. They perform the Boolean  
functions Y = A B or Y = A + B in positive logic.  
2B  
2Y  
GND  
8
The  
SN54ALS08  
and  
SN54AS08  
are  
characterized for operation over the full military  
temperature range of 55°C to 125°C. The  
SN74ALS08andSN74AS08arecharacterizedfor  
operation from 0°C to 70°C.  
SN54ALS08, SN54AS08 . . . FK PACKAGE  
(TOP VIEW)  
FUNCTION TABLE  
(each gate)  
3
2
1
20 19  
18  
1Y  
NC  
2A  
4
5
6
7
8
4A  
NC  
4Y  
NC  
3B  
INPUTS  
OUTPUT  
Y
17  
16  
15  
14  
A
B
H
X
L
H
L
H
L
L
NC  
2B  
9 10 11 12 13  
X
NC – No internal connection  
logic symbol  
logic diagram (positive logic)  
1
1
1A  
2
1A  
2
3
6
&
3
6
8
1Y  
2Y  
3Y  
4Y  
1Y  
2Y  
3Y  
4Y  
1B  
1B  
4
4
2A  
5
2A  
5
2B  
9
2B  
9
3A  
3A  
10  
3B  
12  
4A  
13  
4B  
8
10  
3B  
12  
4A  
11  
11  
13  
4B  
This symbol is in accordance with ANSI/IEEE Std 91-1984 and  
IEC Publication 617-12.  
Pin numbers shown are for the D, J, and N packages.  
Copyright 1994, Texas Instruments Incorporated  
PRODUCTION DATA information is current as of publication date.  
Products conform to specifications per the terms of Texas Instruments  
standard warranty. Production processing does not necessarily include  
testing of all parameters.  
1
POST OFFICE BOX 655303 DALLAS, TEXAS 75265  

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