Datasheet > 逻辑 > 触发器/锁存器> JM38510/37103B2A

JM38510/37103B2A

更新时间： 2024-11-06 11:07:59

品牌	Logo	应用领域
德州仪器 - TI		触发器锁存器
页数	文件大小	规格书
6页	99K
描述
具有清零和预置端的双路负边沿触发式 J-K 触发器 \| FK \| 20 \| -55 to 125

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数据手册

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JM38510/37103B2A 数据手册

SN54ALS112A, SN74ALS112A

DUAL J-K NEGATIVE-EDGE-TRIGGERED FLIP-FLOPS

WITH CLEAR AND PRESET

SDAS199A – APRIL 1982 – REVISED DECEMBER 1994

SN54ALS112A . . . J PACKAGE

SN74ALS112A . . . D OR N PACKAGE

(TOP VIEW)

• Fully Buffered to Offer Maximum Isolation

From External Disturbance

• Package Options Include Plastic

Small-Outline (D) Packages, Ceramic Chip

Carriers (FK), and Standard Plastic (N) and

Ceramic (J) 300-mil DIPs

1CLK

1CLR

2CLR

2CLK

1PRE

TYPICAL MAXIMUM TYPICAL POWER

CLOCK

FREQUENCY

(MHz)

DISSIPATION

PER FLIP-FLOP

(mW)

TYPE

11 2J

2PRE

GND

′ALS112A

description

SN54ALS112A . . . FK PACKAGE

(TOP VIEW)

These devices contain two independent J-K

negative-edge-triggered flip-flops. A low level at

the preset (PRE) or clear (CLR) inputs sets or

resets the outputs, regardless of the levels of the

other inputs. When PRE and CLR are inactive

(high), data at the J and K inputs meeting the

setup-time requirements is transferred to the

outputs on the negative-going edge of the clock

pulse (CLK). Clock triggering occurs at a voltage

level and is not directly related to the fall time of the

clock pulse. Following the hold-time interval, data

at the J and K inputs may be changed without

affecting the levels at the outputs. These versatile

flip-flops can perform as toggle flip-flops by tying

J and K high.

1 20 19

1PRE

2CLR

2CLK

9 10 11 12 13

NC – No internal connection

The SN54ALS112A is characterized for operation over the full military temperature range of –55°C to 125°C.

The SN74ALS112A is characterized for operation from 0°C to 70°C.

FUNCTION TABLE

(each flip-flop)

INPUTS

OUTPUTS

PRE

CLR

CLK

†

↓

Toggle

†

The output levels in this configuration may not meet the

minimum levels for V . Furthermore, this configuration is

nonstable; that is, it does not persist when either PRE or

CLR returns to its inactive (high) level.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of Texas Instruments

standard warranty. Production processing does not necessarily include

testing of all parameters.

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

12 3 4 5 6

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与JM38510/37103B2A相关器件

型号	品牌	获取价格	描述	数据表
JM38510/37103BEA	TI	获取价格	具有清零和预置端的双路负边沿触发式 J-K 触发器 \| J \| 16 \| -55 to 1
JM38510/37104B2A	TI	获取价格	具有三态输出的八路边沿触发式 D 型触发器 \| FK \| 20 \| -55 to 125
JM38510/37104BRA	TI	获取价格	具有三态输出的八路边沿触发式 D 型触发器 \| J \| 20 \| -55 to 125
JM38510/37201B2A	TI	获取价格	HEX/QUADRUPLE D-TYPE FLIP-FLOPS WITH CLEAR
JM38510/37201BEA	TI	获取价格	HEX/QUADRUPLE D-TYPE FLIP-FLOPS WITH CLEAR
JM38510/37202B2A	TI	获取价格	HEX/QUADRUPLE D-TYPE FLIP-FLOPS WITH CLEAR
JM38510/37202BEA	TI	获取价格	HEX/QUADRUPLE D-TYPE FLIP-FLOPS WITH CLEAR
JM38510/37203B2A	TI	获取价格	OCTAL TRANSPARENT D-TYPE LATCHES WITH 3-STATE OUTPUTS
JM38510/37203BRA	TI	获取价格	OCTAL TRANSPARENT D-TYPE LATCHES WITH 3-STATE OUTPUTS
JM38510/37204B2A	TI	获取价格	OCTAL D-TYPE EDGE-TRIGGERED FLIP-FLOPS WITH 3-STATE OUTPUTS

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