Datasheet > 逻辑 > 触发器/锁存器> JM38510/37101BCA

JM38510/37101BCA

更新时间： 2024-09-16 11:07:59

品牌	Logo	应用领域
德州仪器 - TI		触发器锁存器
页数	文件大小	规格书
7页	116K
描述
具有清零和预置端的双路正边沿触发式 D 型触发器 \| J \| 14 \| -55 to 125

阅读下载

中文翻译

获取价格

数据手册
替代型号

如果您发现信息不准确，欢迎纠错

JM38510/37101BCA 数据手册

SN54ALS74A, SN54AS74A, SN74ALS74A, SN74AS74A

DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOPS

WITH CLEAR AND PRESET

SDAS143C – APRIL 1982 – REVISED AUGUST 1995

SN54ALS74A, SN54AS74A . . . J PACKAGE

SN74ALS74A, SN74AS74A . . . D OR N PACKAGE

• Package Options Include Plastic

Small-Outline (D) Packages, Ceramic Chip

Carriers (FK), and Standard Plastic (N) and

Ceramic (J) 300-mil DIPs

(TOP VIEW)

1CLR

1CLK

1PRE

2CLR

TYPICAL MAXIMUM

CLOCK FREQUENCY

TYPICAL POWER

DISSIPATION

PER FLIP-FLOP

(mW)

TYPE

2CLK

2PRE

(C = 50 pF)

(MHz)

′ALS74A

′AS74A

GND

134

description

SN54ALS74A, SN54AS74A . . . FK PACKAGE

(TOP VIEW)

These devices contain two independent

positive-edge-triggered D-type flip-flops. A low

level at the preset (PRE) or clear (CLR) inputs sets

or resets the outputs regardless of the levels of the

other inputs. When PRE and CLR are inactive

(high), data at the data (D) input meeting the

setup-time requirements are transferred to the

outputs on the positive-going edge of the clock

(CLK) pulse. Clock triggering occurs at a voltage

level and is not directly related to the rise time of

CLK. Following the hold-time interval, data at the

D input can be changed without affecting the

levels at the outputs.

20 19

1CLK

17 NC

1PRE

2CLK

2PRE

9 10 11 12 13

NC – No internal connection

The SN54ALS74A and SN54AS74A are

characterized for operation over the full military

temperature range of –55°C to 125°C. The

SN74ALS74AandSN74AS74Aarecharacterized

for operation from 0°C to 70°C.

FUNCTION TABLE

INPUTS

OUTPUTS

PRE

CLR

CLK

†

↑

†

The output levels in this configuration are not

specifiedtomeettheminimumlevelsforV ifthe

lows at PRE and CLR are near V maximum.

Furthermore, this configuration is nonstable; that

is, it does not persist when PRE or CLR returns to

its inactive (high) level.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of Texas Instruments

standard warranty. Production processing does not necessarily include

testing of all parameters.

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

12 3 4 5 6 7

中文翻译

下载PDF

JM38510/37101BCA 替代型号

型号	品牌	替代类型	描述	数据表
M38510/37101B2A	TI	类似代替	具有清零和预置端的双路正边沿触发式 D 型触发器 \| FK \| 20 \| -55 to 1
SNJ54ALS74AFK	TI	类似代替	DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOPS WITH CLEAR AND PRESET
SN74AC74N	TI	功能相似	DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOPS WITH CLEAR AND PRESET

与JM38510/37101BCA相关器件

型号	品牌	获取价格	描述	数据表
JM38510/37102B2A	TI	获取价格	DUAL J-K POSITIVE-EDGE-TRIGGERED FLIP-FLOPS WITH CLEAR AND PRESET
JM38510/37102BEA	TI	获取价格	DUAL J-K POSITIVE-EDGE-TRIGGERED FLIP-FLOPS WITH CLEAR AND PRESET
JM38510/37103B2A	TI	获取价格	具有清零和预置端的双路负边沿触发式 J-K 触发器 \| FK \| 20 \| -55 to
JM38510/37103BEA	TI	获取价格	具有清零和预置端的双路负边沿触发式 J-K 触发器 \| J \| 16 \| -55 to 1
JM38510/37104B2A	TI	获取价格	具有三态输出的八路边沿触发式 D 型触发器 \| FK \| 20 \| -55 to 125
JM38510/37104BRA	TI	获取价格	具有三态输出的八路边沿触发式 D 型触发器 \| J \| 20 \| -55 to 125
JM38510/37201B2A	TI	获取价格	HEX/QUADRUPLE D-TYPE FLIP-FLOPS WITH CLEAR
JM38510/37201BEA	TI	获取价格	HEX/QUADRUPLE D-TYPE FLIP-FLOPS WITH CLEAR
JM38510/37202B2A	TI	获取价格	HEX/QUADRUPLE D-TYPE FLIP-FLOPS WITH CLEAR
JM38510/37202BEA	TI	获取价格	HEX/QUADRUPLE D-TYPE FLIP-FLOPS WITH CLEAR

与JM38510/37101BCA相关文章

摩尔斯微电子在美国约书亚树国家公园测试 Wi-Fi HaLow
2024-09-18

6
贸泽上架Tallysman TW5386智能GNSS天线
2024-09-18

6
SL74HC10N：高性能三输入与非门解析
2024-09-03

84
AIC1781A 电池充电控制器深度解析
2024-09-03

78

产品中心

服务支持

精选活动

关于我们

帮助中心

JM38510/37101BCA

JM38510/37101BCA 数据手册

JM38510/37101BCA 替代型号

与JM38510/37101BCA相关器件

与JM38510/37101BCA相关文章

您还可以找

产品中心

服务支持

精选活动

关于我们

帮助中心

JM38510/37101BCA

JM38510/37101BCA 数据手册

JM38510/37101BCA 替代型号

与JM38510/37101BCA相关器件

与JM38510/37101BCA相关文章

您还可以找

您在本页遇到什么问题？