5秒后页面跳转
捷配首页

Datasheet > 逻辑 > 总线驱动器/收发器> JM38510/32502BSA
JM38510/32502BSA PDF预览

JM38510/32502BSA

更新时间： 2024-11-22 22:41:07
品牌 Logo 应用领域
德州仪器 - TI 触发器锁存器
页数 文件大小 规格书
16页 241K
描述
OCTAL D-TYPE TRANSPARENT LATCHES AND EDGE-TRIGGERED FLIP-FLOPS

阅读下载

中文翻译

获取价格

JM38510/32502BSA 技术参数

是否无铅： 不含铅是否Rohs认证： 不符合
生命周期：Active零件包装代码：DFP
包装说明：DFP,针数：20
Reach Compliance Code：not_compliantHTS代码：8542.39.00.01
Factory Lead Time：1 week风险等级：1.39
系列：LSJESD-30 代码：R-GDFP-F20
JESD-609代码：e0长度：13.09 mm
逻辑集成电路类型：BUS DRIVER最大I（ol）：0.024 A
位数：8功能数量：1
端口数量：2端子数量：20
最高工作温度：125 °C最低工作温度：-55 °C
输出特性：3-STATE输出极性：TRUE
封装主体材料：CERAMIC, GLASS-SEALED封装代码：DFP
封装形状：RECTANGULAR封装形式：FLATPACK
峰值回流温度（摄氏度）：NOT SPECIFIED最大电源电流（ICC）：40 mA
传播延迟（tpd）：30 ns认证状态：Not Qualified
筛选级别：MIL-M-38510 Class B座面最大高度：2.54 mm
最大供电电压 (Vsup)：5.5 V最小供电电压 (Vsup)：4.5 V
标称供电电压 (Vsup)：5 V表面贴装：YES
技术：TTL温度等级：MILITARY
端子面层：Tin/Lead (Sn/Pb)端子形式：FLAT
端子节距：1.27 mm端子位置：DUAL
处于峰值回流温度下的最长时间：NOT SPECIFIED宽度：7.62 mm

JM38510/32502BSA 数据手册

 浏览型号JM38510/32502BSA的Datasheet PDF文件第2页浏览型号JM38510/32502BSA的Datasheet PDF文件第3页浏览型号JM38510/32502BSA的Datasheet PDF文件第4页浏览型号JM38510/32502BSA的Datasheet PDF文件第5页浏览型号JM38510/32502BSA的Datasheet PDF文件第6页浏览型号JM38510/32502BSA的Datasheet PDF文件第7页 
SN54LS373, SN54LS374, SN54S373, SN54S374,  
SN74LS373, SN74LS374, SN74S373, SN74S374  
OCTAL D-TYPE TRANSPARENT LATCHES AND EDGE-TRIGGERED FLIP-FLOPS  
SDLS165B – OCTOBER 1975 – REVISED AUGUST 2002  
SN54LS373, SN54LS374, SN54S373,  
SN54S374 . . . J OR W PACKAGE  
SN74LS373, SN74S374 . . . DW, N, OR NS PACKAGE  
Choice of Eight Latches or Eight D-Type  
Flip-Flops in a Single Package  
3-State Bus-Driving Outputs  
Full Parallel Access for Loading  
Buffered Control Inputs  
SN74LS374 . . . DB, DW, N, OR NS PACKAGE  
SN74S373 . . . DW OR N PACKAGE  
(TOP VIEW)  
1
2
3
4
5
6
7
8
9
10  
20  
19  
18  
17  
16  
15  
14  
13  
12  
11  
OC  
1Q  
V
CC  
Clock-Enable Input Has Hysteresis to  
Improve Noise Rejection (’S373 and ’S374)  
8Q  
8D  
7D  
7Q  
6Q  
6D  
5D  
5Q  
1D  
P-N-P Inputs Reduce DC Loading on Data  
Lines (’S373 and ’S374)  
2D  
2Q  
3Q  
description  
3D  
These 8-bit registers feature 3-state outputs  
designed specifically for driving highly capacitive  
or relatively low-impedance loads. The  
4D  
4Q  
†
GND  
C
high-impedance  
3-state  
and  
increased  
†
Cfor’LS373and’S373;CLKfor’LS374and’S374.  
high-logic-level drive provide these registers with  
the capability of being connected directly to and  
driving the bus lines in a bus-organized system  
without need for interface or pullup components.  
These devices are particularly attractive for  
implementing buffer registers, I/O ports,  
bidirectional bus drivers, and working registers.  
SN54LS373, SN54LS374, SN54S373,  
SN54S374 . . . FK PACKAGE  
(TOP VIEW)  
3
2
1
20 19  
18  
The eight latches of the ’LS373 and ’S373 are  
transparent D-type latches, meaning that while  
the enable (C or CLK) input is high, the Q outputs  
follow the data (D) inputs. When C or CLK is taken  
low, the output is latched at the level of the data  
that was set up.  
8D  
7D  
7Q  
6Q  
6D  
2D  
2Q  
3Q  
3D  
4D  
4
5
6
7
8
17  
16  
15  
14  
9 10 11 12 13  
The eight flip-flops of the ’LS374 and ’S374 are  
edge-triggered D-type flip-flops. On the positive  
transition of the clock, the Q outputs are set to the  
logic states that were set up at the D inputs.  
†
Cfor’LS373and’S373;CLKfor’LS374and’S374.  
Schmitt-trigger buffered inputs at the enable/clock lines of the ’S373 and ’S374 devices simplify system design  
as ac and dc noise rejection is improved by typically 400 mV due to the input hysteresis. A buffered  
output-control (OC) input can be used to place the eight outputs in either a normal logic state (high or low logic  
levels) or the high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus lines  
significantly.  
OC does not affect the internal operation of the latches or flip-flops. That is, the old data can be retained or new  
data can be entered, even while the outputs are off.  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
Copyright 2002, Texas Instruments Incorporated  
On products compliant to MIL-PRF-38535, all parameters are tested  
PRODUCTION DATA information is current as of publication date.  
Products conform to specifications per the terms of Texas Instruments  
standard warranty. Production processing does not necessarily include  
unless otherwise noted. On all other products, production  
testing of all parameters.  
processing does not necessarily include testing of all parameters.  
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265  
1234567...16

中文翻译

下载PDF

JM38510/32502BSA 替代型号

型号 品牌 替代类型 描述 数据表
M38510/32502SSA TI

完全替代

 具有三态输出的八路 D 类透明锁存器 | W | 20 | -55 to 125
JM38510/32502SSA TI

完全替代

 OCTAL D-TYPE TRANSPARENT LATCHES AND EDGE-TRIGGERED FLIP-FLOPS

与JM38510/32502BSA相关器件

型号 品牌 获取价格 描述 数据表
JM38510/32502SRA TI

获取价格

 		OCTAL D-TYPE TRANSPARENT LATCHES AND EDGE-TRIGGERED FLIP-FLOPS
JM38510/32502SSA TI

获取价格

 		OCTAL D-TYPE TRANSPARENT LATCHES AND EDGE-TRIGGERED FLIP-FLOPS
JM38510/32503B2A TI

获取价格

 		OCTAL D-TYPE TRANSPARENT LATCHES AND EDGE-TRIGGERED FLIP-FLOPS
JM38510/32503B2A MOTOROLA

获取价格

 		LS SERIES, 8-BIT DRIVER, TRUE OUTPUT, CQCC20, CERAMIC, LCC-20
JM38510/32503BRA MOTOROLA

获取价格

 		Bus Driver, LS Series, 1-Func, 8-Bit, True Output, TTL, CDIP20, CERDIP-20
JM38510/32503BRA TI

获取价格

 		OCTAL D-TYPE TRANSPARENT LATCHES AND EDGE-TRIGGERED FLIP-FLOPS
JM38510/32503BSA TI

获取价格

 		OCTAL D-TYPE TRANSPARENT LATCHES AND EDGE-TRIGGERED FLIP-FLOPS
JM38510/32503BSA MOTOROLA

获取价格

 		LS SERIES, 8-BIT DRIVER, TRUE OUTPUT, CDFP20, CERAMIC, FP-20
JM38510/32504B2A TI

获取价格

 		OCTAL, HEX, AND QUAD D-TYPE FLIP-FLOPS WITH ENABLE
JM38510/32504BRA TI

获取价格

 		OCTAL, HEX, AND QUAD D-TYPE FLIP-FLOPS WITH ENABLE

与JM38510/32502BSA相关文章

您还可以找


热门产品
PCB打样/小批量
铝基板
BOM智能配单
PCBA制造
钣金
精密CNC
模具注塑
薄膜开关
精选活动
PCBA打样特惠
四六层板品质升级
铝基板品质升级
一体化电子制造
DFM下载
服务支持
企业认证
产品展示
工厂展示
工艺能力
积分商城
关于捷配
捷配简介
企业文化
公司动态
人才招聘
联系我们
帮助中心
下单流程
付款流程
开票流程
常见问题
全球PCB制造服务专线 400-613-0088

工作时间：9:00-21:00

CEO邮箱：ceo@jiepei.com

投诉邮箱：tousu@jiepei.com

捷配网-微信公众号 微信公众号
捷配网-微信公众号 抖音公众号
资质认证：
合作快递：
支付方式：
Copyright © 2024 Jiepei.com Inc. All Rights Reserved. 版权所有:杭州捷配信息科技有限公司 浙公网安备 33010502006866号 浙ICP备10014259号-119 营业执照ICP证