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JM38510/11103BEA

更新时间： 2024-01-08 14:02:56
品牌 Logo 应用领域
TEMIC 驱动器开关
页数 文件大小 规格书
8页 115K
描述
High-Speed Drivers with Dual DPST JFET Switches

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中文翻译

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JM38510/11103BEA 技术参数

生命周期：Transferred包装说明：,
Reach Compliance Code：unknown风险等级：5.55
Is Samacsys：N模拟集成电路 - 其他类型：DPST
JESD-30 代码：R-CDIP-T16标称负供电电压 (Vsup)：-15 V
信道数量：2功能数量：2
端子数量：16标称断态隔离度：50 dB
最大通态电阻 (Ron)：30 Ω最高工作温度：125 °C
最低工作温度：-55 °C封装主体材料：CERAMIC, METAL-SEALED COFIRED
封装形状：RECTANGULAR封装形式：IN-LINE
认证状态：Not Qualified最大供电电流 (Isup)：4.5 mA
标称供电电压 (Vsup)：15 V表面贴装：NO
最长断开时间：130 ns最长接通时间：150 ns
技术：JFET温度等级：MILITARY
端子形式：THROUGH-HOLE端子位置：DUAL
Base Number Matches：1

JM38510/11103BEA 数据手册

 浏览型号JM38510/11103BEA的Datasheet PDF文件第2页浏览型号JM38510/11103BEA的Datasheet PDF文件第3页浏览型号JM38510/11103BEA的Datasheet PDF文件第4页浏览型号JM38510/11103BEA的Datasheet PDF文件第5页浏览型号JM38510/11103BEA的Datasheet PDF文件第6页浏览型号JM38510/11103BEA的Datasheet PDF文件第7页 
DG183/184/185  
High-Speed Drivers with Dual DPST JFET Switches  
Features  
Benefits  
Applications  
D Constant On-Resistance Over  
D Low Distortion  
D Audio Switching  
D Precision Switching  
D Video Switching  
D Video Routing  
D Sample/Hold  
Entire Analog Range  
D Eliminates Large Signal Errors  
D High Precision  
D Low Leakage  
D Low Crosstalk  
D Improved Channel Isolation  
D Break-Before-Make Switching  
D Rad Hardness  
D Eliminates Inadvertent Shorting  
Between Channels  
D Aerospace  
D Fault Protection  
Description  
The DG183/184/185 are precision dual double-pole, on-resistance include audio switching, video switching, and  
single-throw (DPST) analog switches designed to provide data acquisition.  
accurate switching of video and audio signals. This series  
is ideally suited for applications requiring a constant  
on-resistance over the entire analog range.  
To achieve fast and accurate switch performance, each  
device comprises four n-channel JFET transistors and a  
The major difference in the devices is the on-resistance TTL compatible bipolar driver. In the on state, each switch  
(DG183—10 W, DG184—30 W, DG185—75 W). Reduced conducts current equally well in either direction. In the off  
errors are achieved through low leakage current (I  
condition, the switches will block up to 20 V peak-to-peak,  
D(on)  
< 2 nA). Applications which benefit from the flat JFET with feedthrough of less than –60 dB at 10 MHz.  
Functional Block Diagram and Pin Configuration  
D
S
1
1
1
2
3
4
5
6
7
8
16  
15  
14  
13  
12  
11  
10  
9
1
2
3
4
5
6
7
14  
13  
12  
11  
10  
9
S
D
S
3
4
4
2
2
2
NC  
IN  
1
D
D
S
3
1
D
S
V–  
3
3
4
4
D
Flat  
Package  
V
S
R
1
Dual-In-Line  
Top View  
Top View  
IN  
IN  
1
S
V
L
V+  
V–*  
D
V+  
8
V
V
R
L
NC  
IN  
2
Refer to JAN38510 Information, Military Section  
*Common to Substrate and Case  
D
S
2
2
Truth Table  
Logic  
0
1
Switch  
OFF  
ON  
Logic “0”  
0.8 V  
Logic “1”
w
2.0 V  
Updates to this data sheet may be obtained via facsimile by calling Siliconix FaxBack, 1-408-970-5600. Please request FaxBack document #70032.  
Siliconix  
1
S-52895—Rev. D, 16-Jun-97  
12345678

中文翻译

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