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JLC1562BFL2 PDF预览

JLC1562BFL2

更新时间: 2024-01-30 19:19:11
品牌 Logo 应用领域
安森美 - ONSEMI 光电二极管
页数 文件大小 规格书
8页 80K
描述
IC,I2C BUS EXTENDER,SOP,16PIN,PLASTIC

JLC1562BFL2 技术参数

是否Rohs认证: 不符合生命周期:Obsolete
Reach Compliance Code:not_compliant风险等级:5.92
JESD-30 代码:R-PDSO-G16JESD-609代码:e0
端子数量:16最高工作温度:85 °C
最低工作温度:-40 °C封装主体材料:PLASTIC/EPOXY
封装代码:SOP封装等效代码:SOP16,.3
封装形状:RECTANGULAR封装形式:SMALL OUTLINE
电源:5 V认证状态:Not Qualified
子类别:Other Interface ICs最大压摆率:5 mA
标称供电电压:5 V表面贴装:YES
温度等级:INDUSTRIAL端子面层:Tin/Lead (Sn/Pb)
端子形式:GULL WING端子节距:1.27 mm
端子位置:DUALBase Number Matches:1

JLC1562BFL2 数据手册

 浏览型号JLC1562BFL2的Datasheet PDF文件第2页浏览型号JLC1562BFL2的Datasheet PDF文件第3页浏览型号JLC1562BFL2的Datasheet PDF文件第4页浏览型号JLC1562BFL2的Datasheet PDF文件第5页浏览型号JLC1562BFL2的Datasheet PDF文件第6页浏览型号JLC1562BFL2的Datasheet PDF文件第7页 
JLC1562B  
I2C Bus I/O Expander  
The JLC1562B facilitates easy I2C Bus expandibility. Multiple  
devices (up to 8 on the same I2C Bus) are easily added as each device  
has its own selectable 3-bit address. The JLC1562B provides an 8-bit  
bidirectional input/output port and 6-bit resolution Digital to Analog  
Converter. The voltage on pins P0-P4 is compared with a controllable  
threshold voltage and the results are readable through the I2C Bus.  
I2C Bus interface pins SDA, SCL and A0-A2 are; Serial Data,  
Serial Clock and Device Address respectively. External interface pins  
are P0-P7 and VDAC; I/O Port and D/A output.  
http://onsemi.com  
MARKING  
DIAGRAMS  
16  
PDIP-16  
N SUFFIX  
CASE 648  
Features  
JLC1562BN  
AWLYYWW  
Low Power Dissipation  
I2C-Bus Format (2-Wire Type; SDA, SCL) Data Transfer  
6-bit DAC  
1
16  
Bus Address Selectable (3-bit)  
EIAJ-16  
F SUFFIX  
CASE 966  
JLC1562B  
ALYW  
Address Input Pins are Pulled Up to Vdd with Internal Resistor  
I/O Pins are Open Drain Outputs  
5 Comparators at Inputs  
1
A
= Assembly Location  
WL, L = Wafer Lot  
YY, Y = Year  
Inputs Protected from External Bus Currents in Power Down Mode  
WW, W = Work Week  
PIN ASSIGNMENT  
Power-On  
Reset  
A0  
A1  
A2  
P0  
P1  
P2  
P3  
1
2
3
4
5
6
7
8
16  
V
DD  
15 SDA  
14 SCL  
13 VDAC  
12 P7  
P7  
SDA  
SCL  
P6  
P5  
P4  
P3  
P2  
P1  
P0  
8 Bit  
11 P6  
6 Bit  
10 P5  
Latch  
V
DD  
V
9
P4  
SS  
6-Bit  
DAC  
PIN LIST  
A0-A2  
Chip Address Input  
A0  
A1  
A2  
P0-P4  
P5-P7  
SCL  
Comparator Input / Open Drain Output  
Comparator Input / Open Drain Output  
Serial Clock Input  
1/2 V  
CC  
3 Bit  
Comp.  
A
SDA  
I2C Data Output  
(C5-C7)  
VDAC  
DAC Output  
5 Bit  
5 Bit  
(C0-C4)  
Comp.  
B
ORDERING INFORMATION  
Device  
Package  
PDIP-16  
EIAJ-16  
EIAJ-16  
Shipping  
500 / Unit Pak  
50 Units / Rail  
2000 Units / Reel  
NOTE: Internal Power On Reset sets P0 P7 low, sets VDAC to 1/80 V  
DD  
and selects 1/2 V for Comparator “B” threshold.  
JLC1562BN  
JLC1562BF  
JLC1562BFEL  
DD  
Figure 1. Block Diagram  
Semiconductor Components Industries, LLC, 2002  
1
Publication Order Number:  
November, 2002 - Rev. 2  
JLC1562BE/D  

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