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JANTXVR2N7494U5 PDF预览

JANTXVR2N7494U5

更新时间: 2024-11-21 08:29:59
品牌 Logo 应用领域
英飞凌 - INFINEON /
页数 文件大小 规格书
25页 222K
描述
Power Field-Effect Transistor, 12A I(D), 30V, 1-Element, N-Channel, Silicon, Metal-oxide Semiconductor FET, LCC-18

JANTXVR2N7494U5 数据手册

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INCH-POUND  
The documentation and process conversion  
measures necessary to comply with this revision  
shall be completed by 3 August 2011.  
MIL-PRF-19500/700B  
3 May 2011  
SUPERSEDING  
MIL-PRF-19500/700A  
27 January 2005  
PERFORMANCE SPECIFICATION SHEET  
SEMICONDUCTOR DEVICE, FIELD EFFECT RADIATION HARDENED  
(TOTAL DOSE AND SINGLE EVENT EFFECTS) TRANSISTOR, N-CHANNEL,  
SILICON, TYPES 2N7494U5, 2N7495U5, AND 2N7496U5,  
JANTXVR, F, G, AND H, AND JANSR, F, G, AND H  
This specification is approved for use by all Departments  
and Agencies of the Department of Defense.  
The requirements for acquiring the product described herein shall consist of  
this specification sheet and MIL-PRF-19500.  
1. SCOPE  
1.1 Scope. This specification covers the performance requirements for a N-channel, enhancement-mode,  
MOSFET, radiation hardened (Total Dose and Single Event Effects (SEE)), power transistor. Two levels of product  
assurance are provided for each device type as specified in MIL-PRF-19500, with avalanche energy maximum rating  
(EAS) and maximum avalanche current (IAS).  
1.2 Physical dimensions. See figure 1, (surface mount, LCC-18).  
*
1.3 Maximum ratings. TA = +25°C, unless otherwise specified.  
Type  
PT (1)  
TC =  
+25°C  
PT  
TA =  
+25°C  
VDS  
VDG  
VGS  
ID1 (3) (4)  
TC =+25°C  
ID2 (3) (4)  
TC =  
+100°C  
IS  
IDM (5)  
A (pk)  
TJ  
and  
TSTG  
R θ  
JC  
(2)  
W
W
V dc  
V dc  
V dc  
A dc  
A dc  
A dc  
°C/W  
°C  
2N7494U5  
2N7495U5  
2N7496U5  
25  
1.67  
30  
60  
30  
60  
12  
11.7  
10  
8
12  
12  
10  
48  
46.8  
40  
5.0  
±20  
±20  
±20  
-55  
to  
+150  
7.4  
6.5  
100  
100  
*
*
(1) Derate linearly by 0.2 W/°C for TC > +25°C.  
(2) See figure 2, thermal impedance curves.  
(3) The following formula derives the maximum theoretical ID limit. ID is limited by package and internal  
construction to 12 amps.  
-
TJM TC  
( on ) at  
TJM  
=
ID  
(
)
x
(
)
RθJC  
RDS  
*
(4) See figure 3, maximum drain current graph.  
(5) IDM = 4 X ID1 as calculated in note (3).  
Comments, suggestions, or questions on this document should be addressed to DLA Land and Maritime,  
ATTN: VAC, P.O. Box 3990, Columbus, OH 43218-3990, or emailed to Semiconductor@dla.mil. Since contact  
information can change, you may want to verify the currency of this address information using the ASSIST  
Online database at https://assist.daps.dla.mil/.  
AMSC N/A  
FSC 5961  
 

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