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JANSR2N7424 PDF预览

JANSR2N7424

更新时间: 2024-11-06 11:01:15
品牌 Logo 应用领域
英飞凌 - INFINEON 局域网脉冲晶体管
页数 文件大小 规格书
22页 232K
描述
Rad hard, -60V, -35A, single, P-channel MOSFET, R4 in a TO-254AA package - TO-254AA, 100 krad(Si) TID, QPL

JANSR2N7424 技术参数

是否Rohs认证:不符合生命周期:Active
包装说明:,Reach Compliance Code:compliant
风险等级:5.76Is Samacsys:N
峰值回流温度(摄氏度):NOT SPECIFIED认证状态:Qualified
处于峰值回流温度下的最长时间:NOT SPECIFIEDBase Number Matches:1

JANSR2N7424 数据手册

 浏览型号JANSR2N7424的Datasheet PDF文件第2页浏览型号JANSR2N7424的Datasheet PDF文件第3页浏览型号JANSR2N7424的Datasheet PDF文件第4页浏览型号JANSR2N7424的Datasheet PDF文件第5页浏览型号JANSR2N7424的Datasheet PDF文件第6页浏览型号JANSR2N7424的Datasheet PDF文件第7页 
The documentation and process conversion measures  
necessary to comply with this document shall be  
completed by 6 February 2014.  
INCH-POUND  
MIL-PRF-19500/660E  
6 December 2013  
SUPERSEDING  
MIL-PRF-19500/660D  
11 February 2013  
PERFORMANCE SPECIFICATION SHEET  
SEMICONDUCTOR DEVICE, FIELD EFFECT RADIATION HARDENED  
TRANSISTOR, P-CHANNEL SILICON, TYPES 2N7424, 2N7425, AND 2N7426,  
JANTXVR, JANTXVF, JANSR, AND JANSF  
This specification is approved for use by all Departments  
and Agencies of the Department of Defense.  
The requirements for acquiring the product described herein shall consist of  
this specification sheet and MIL-PRF-19500.  
1. SCOPE  
1.1 Scope. This specification covers the performance requirements for a P-channel, enhancement-mode,  
MOSFET, radiation hardened, power transistor. Two levels of product assurance are provided for each device type  
as specified in MIL-PRF-19500, with avalanche energy maximum rating (EAS) and maximum avalanche current (IAS).  
See 6.5 for JANHC and JANKC die versions.  
1.2 Physical dimensions. See figure 1, TO-254AA.  
1.3 Maximum ratings. Unless otherwise specified, TA = +25oC.  
Type  
PT (1)  
TC =  
+25°C  
PT  
TA =  
+25°C  
VDS  
VDG  
VGS  
ID1 (3) (4) ID2 (3)(4)  
IS  
IDM  
(5)  
TJ  
and  
TSTG  
R θJC  
(2)  
TC =  
TC =+25°C  
+100°C  
W
W
V dc  
V dc  
V dc  
A dc  
A dc  
A dc  
A (pk)  
°C/W  
°C  
2N7424  
2N7425  
2N7426  
250  
250  
250  
3.0  
3.0  
3.0  
-60  
-60  
-35  
-35  
-27  
-30  
-24  
-17  
-35  
-35  
-27  
-140  
-140  
-108  
0.50  
0.50  
0.50  
±20  
±20  
±20  
-55  
to  
+150  
-100  
-200  
-100  
-200  
(1) Derate linearly 2.0 W/°C for TC > +25°C.  
(2) See figure 2, thermal impedance curves.  
(3) The following formula derives the maximum theoretical ID limit. ID is limited by package and internal  
construction.  
-
TJM TC  
( on ) at  
TJM  
=
ID  
(
)
x
(
)
RθJC  
RDS  
(4) See figure 3, maximum drain current graphs.  
(5) IDM = 4 x ID1 as calculated in note 3.  
Comments, suggestions, or questions on this document should be addressed to DLA Land and Maritime,  
ATTN: VAC, P.O. Box 3990, Columbus, OH 43218-3990, or emailed to Semiconductor@dla.mil. Since contact  
information can change, you may want to verify the currency of this address information using the ASSIST  
Online database at https://assist.dla.mil.  
AMSC N/A  
FSC 5961  
 

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