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JANKCDF2N2906A

更新时间: 2024-09-28 08:56:55
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美高森美 - MICROSEMI /
页数 文件大小 规格书
35页 798K
描述
Transistor,

JANKCDF2N2906A 数据手册

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The documentation and process conversion measures  
necessary to comply with this document shall be  
completed by 16 May 2013.  
INCH-POUND  
MIL-PRF-19500/291U  
16 February 2013  
SUPERSEDING  
MIL-PRF-19500/291T  
23 September 2011  
PERFORMANCE SPECIFICATION SHEET  
* SEMICONDUCTOR DEVICE, TRANSISTOR, PNP, SILICON, SWITCHING,  
TYPES 2N2906A, 2N2906AL, 2N2907A, 2N2907AL, 2N2906AUA,  
2N2907AUA, 2N2906AUB, 2N2906AUBC, 2N2907AUB, 2N2907AUBC,  
2N2906AUBN, 2N2906AUBCN, 2N2907AUBN, AND 2N2907AUBCN, JAN,  
JANTX, JANTXV, JANS, JANSM, JANSD, JANSP, JANSL, JANSR, JANSF,  
JANSG, JANSH JANHC, JANKC, JANKCM, JANKCD,  
JANKCP, JANKCL, JANKCR, JANKCF, JANKCG, AND JANKCH  
This specification is approved for use by all Departments  
and Agencies of the Department of Defense.  
The requirements for acquiring the product described herein shall consist of  
this specification sheet and MIL-PRF-19500.  
1. SCOPE  
1.1 Scope. This specification covers the performance requirements for PNP, silicon, switching transistors. Five  
levels of product assurance are provided for each encapsulated device type as specified in MIL-PRF-19500 and two  
levels of product assurance are provided for each unencapsulated device type. Radiation hardness assurance (RHA)  
level designators “M”, “D”, “P“, “L” “R”, “F’, “G”, and “H” are appended to the device prefix to identify devices which  
have passed RHA requirements.  
*
1.2 Physical dimensions. See figure 1 (similar to a TO-18), figure 2, (surface mount case outlines UA, figure 3  
UB (metal lid, as shield, connected to fourth pad), UBC (ceramic lid, braze-ring connected to fourth pad), UBN (3-pin,  
isolated metal lid), and UBCN (3-pin, isolated ceramic lid) and figures 4, and 5 (JANHC and JANKC).  
1.3 Maximum ratings. Unless otherwise specified TA = +25°C.  
Types  
I
V
V
V
T and T  
J
C
CBO  
EBO  
CEO  
STG  
mA dc  
600  
V dc  
60  
V dc  
5
V dc  
60  
°C  
All devices  
-65 to +200  
* Comments, suggestions, or questions on this document should be addressed to DLA Land and Maritime,  
ATTN: VAC, P.O. Box 3990, Columbus, OH 43218-3990, or emailed to Semiconductor@dla.mil. Since contact  
information can change, you may want to verify the currency of this address information using the ASSIST Online  
database at https://assist.dla.mil .  
AMSC N/A  
FSC 5961  
 

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