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J108 PDF预览

J108

更新时间: 2024-02-05 03:24:16
品牌 Logo 应用领域
MICROSS /
页数 文件大小 规格书
1页 283K
描述
Linear Systems replaces discontinued Siliconix J108

J108 技术参数

生命周期:Obsolete零件包装代码:TO-92
包装说明:CYLINDRICAL, O-PBCY-W3针数:3
Reach Compliance Code:unknownHTS代码:8541.21.00.95
风险等级:5.63其他特性:LOW INSERTION LOSS
配置:SINGLE最大漏源导通电阻:8 Ω
FET 技术:JUNCTION最大反馈电容 (Crss):15 pF
JEDEC-95代码:TO-226AAJESD-30 代码:O-PBCY-W3
元件数量:1端子数量:3
工作模式:DEPLETION MODE封装主体材料:PLASTIC/EPOXY
封装形状:ROUND封装形式:CYLINDRICAL
极性/信道类型:N-CHANNEL认证状态:Not Qualified
表面贴装:NO端子形式:WIRE
端子位置:BOTTOM晶体管应用:SWITCHING
晶体管元件材料:SILICONBase Number Matches:1

J108 数据手册

  
J108  
N-CHANNEL JFET  
Linear Systems replaces discontinued Siliconix J108  
FEATURES  
This n-channel JFET is optimised for low noise high  
DIRECT REPLACEMENT FOR SILICONIX J108  
LOW ON RESISTANCE  
FAST SWITCHING  
performance switching. The part is particularly suitable  
for use in low noise audio amplifiers. The SOT-23  
package is well suited for cost sensitive applications  
and mass production.  
rDS(on) 8Ω  
t(on) 4ns  
ABSOLUTE MAXIMUM RATINGS @ 25°C (unless otherwise noted)  
Maximum Temperatures  
(See Packaging Information).  
Storage Temperature  
55°C to +150°C  
55°C to +150°C  
J108 Benefits:  
Operating Junction Temperature  
Maximum Power Dissipation  
Continuous Power Dissipation  
MAXIMUM CURRENT  
ƒ
ƒ
ƒ
Low On Resistance  
Low insertion loss  
Low Noise  
350mW  
J108 Applications:  
Gate Current (Note 1)  
MAXIMUM VOLTAGES  
Gate to Drain Voltage  
50mA  
ƒ
ƒ
ƒ
Analog Switches  
Commutators  
Choppers  
VGDS = 25V  
VGSS = 25V  
Gate to Source Voltage  
J108 ELECTRICAL CHARACTERISTICS @ 25°C (unless otherwise noted)  
SYMBOL  
BVGSS  
VGS(off)  
VGS(F)  
IDSS  
IGSS  
IG  
ID(off)  
rDS(on)  
CHARACTERISTIC  
Gate to Source Breakdown Voltage  
Gate to Source Cutoff Voltage  
Gate to Source Forward Voltage  
Drain to Source Saturation Current (Note 2)  
Gate Reverse Current  
MIN  
25  
3  
‐‐  
80  
‐‐  
‐‐  
‐‐  
‐‐  
TYP.  
‐‐  
‐‐  
0.7  
‐‐  
0.01  
0.01  
0.02  
‐‐  
MAX  
‐‐  
10  
‐‐  
‐‐  
3  
‐‐  
UNITS  
CONDITIONS  
IG = 1µA, VDS = 0V  
VDS = 5V, ID = 1µA  
IG = 1mA, VDS = 0V  
VDS = 15V, VGS = 0V  
VGS = 15V, VDS = 0V  
VDG = 10V, ID = 10mA  
VDS = 5V, VGS = 10V  
VGS = 0V, VDS 0.1V  
V
mA  
nA  
Gate Operating Current  
Drain Cutoff Current  
Drain to Source On Resistance  
3
8
Ω
J108 DYNAMIC ELECTRICAL CHARACTERISTICS @ 25°C (unless otherwise noted)  
SYMBOL  
gfs  
gos  
rDS(on)  
Ciss  
CHARACTERISTIC  
MIN  
‐‐  
TYP.  
17  
0.6  
‐‐  
60  
11  
3.5  
MAX  
‐‐  
UNITS  
mS  
CONDITIONS  
VDS = 5V, ID = 10mA , f = 1kHz  
Forward Transconductance  
Click To Buy  
Output Conductance  
Drain to Source On Resistance  
Input Capacitance  
‐‐  
‐‐  
‐‐  
‐‐  
‐‐  
‐‐  
8
‐‐  
‐‐  
‐‐  
Ω
VGS = 0V, ID = 0A, f = 1kHz  
VDS = 0V, VGS = 0V, f = 1MHz  
VDS = 0V, VGS = 10V, f = 1MHz  
VDS = 5V, ID = 10mA , f = 1kHz  
pF  
nV/Hz  
Crss  
en  
Reverse Transfer Capacitance  
Equivalent Noise Voltage  
J108 SWITCHING CHARACTERISTICS @ 25°C (unless otherwise noted)  
SYMBOL  
td(on)  
tr  
CHARACTERISTIC  
UNITS  
CONDITIONS  
Turn On Time  
3
VDD = 1.5V  
VGS(H) = 0V  
Turn On Rise Time  
Turn Off Time  
1
ns  
td(off)  
tf  
4
See Switching Circuit  
Turn Off Fall Time  
18  
Note 1 Absolute maximum ratings are limiting values above which J108 serviceability may be impaired. Note 2 – Pulse test: PW300 µs, Duty Cycle 3%  
J108 SWITCHING CIRCUIT PARAMETERS  
SWITCHING TEST CIRCUIT  
VGS(L)  
RL  
12V  
150Ω  
10mA  
Available Packages:  
SOT-23 (Top View)  
J108 in SOT-23  
J108 in bare die.  
ID(on)  
Micross Components Europe  
Please contact Micross for full  
package and die dimensions  
Tel: +44 1603 788967  
Email: chipcomponents@micross.com  
Web: http://www.micross.com/distribution  
Information furnished by Linear Integrated Systems and Micross Components is believed to be accurate and reliable. However, no responsibility is assumed for its use; nor for any infringement of patents or  
other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Linear Integrated Systems.  

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