Datasheet > IZ74LV574

IZ74LV574

更新时间： 2024-11-04 23:15:07

品牌	Logo	应用领域
INTEGRAL		触发器
页数	文件大小	规格书
8页	198K
描述
Octal D-type flip-flop; positive edge-trigger (3-State)

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数据手册

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IZ74LV574 数据手册

TECHNICAL DATA

IN74LV574

Octal D-type flip-flop;

positive edge-trigger (3-State)

N SUFFIX

PLASTIC DIP

The 74LV574 is a low-voltage Si-gate CMOS device and is pin and

function compatible with 74HC/HCT574.

The 74LV574 is an octal D-type flip–flop featuring separate D-type

inputs for each flip-flop and non-inverting 3-state outputs for oriented

applications. A clock (CP) and an output enable (OE) input are common

to all flip-flops. The eight flip-flops will store the state of their individual

D-inputs that meet the set-up and hold times requirements on the LOW-

to-HIGH CP transition. When OE is LOW, the contents of the eight flip-

flops are available at the outputs. When OE is HIGH, the outputs go to

the high impedance OFF-state. Operation of the OE input does not affect

the state of the flip-flops.

DW SUFFIX

ORDERING INFORMATION

IN74LV574N

IN74LV574DW

IZ74LV574

Plastic DIP

SOIC

chip

Output voltage levels are compatible with input levels of CMOS,

NMOS and TTL IC_S

T_A= -40° to 125° C for all packages

Supply voltage range: 1.0 to 5.5 V

Low input current: 1.0 mÀ; 0.1 mÀ at Ò = 25 °Ñ

High Noise Immunity Characteristic of CMOS Devices

PIN ASSIGNMENT

LOGIC DIAGRAM

FUNCTION TABLE

Inputs

Clock

Output

Enable

PIN 20=V_CC

PIN 10 = GND

L,H,

change

H= high level

L = low level

X = don’t care

Z = high impedance

INTEGRAL

12 3 4 5 6 7 8

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