Datasheet > IZ74LV273

IZ74LV273

更新时间： 2024-09-14 23:15:07

品牌	Logo	应用领域
INTEGRAL		触发器时钟
页数	文件大小	规格书
7页	135K
描述
Octal D Flip-Flop with Common Clock and Reset

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数据手册

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IZ74LV273 数据手册

TECHNICAL DATA

IN74LV273

Octal D Flip-Flop with Common Clock and Reset

The IN74LV273 is a low-voltage Si-gate CMOS device and is pin and

function compatible with the 74HC/HCT273.

The IN74LV273 has eight edge-triggered, D-type flip-flops with

individual D inputs and Q outputs. The common clock (CP) and master

reset (MR) inputs load and reset (clear) all flip-flops simultaneously. The

N SUFFIX

PLASTIC DIP

state of each D input, one set-up time before the LOW-to-HIGH clock

transition, is transferred to the corresponding output (Qn) of the flip-

DW SUFFIX

flop. All outputs will be forced LOW independently of clock or data

inputs by a LOW voltage level on the MR input. The device is useful for

applications where the true output only is required and the clock and

master reset are common to all storage elements.

Output voltage levels are compatible with input levels of CMOS,

NMOS and TTL IC_S

Supply voltage range: 1.2 to 5.5 V

Low input current: 1.0 mÀ; 0.1 mÀ at Ò = 25 °Ñ

High Noise Immunity Characteristic of CMOS Devices

ORDERING INFORMATION

IN74LV273N

IN74LV273DW

IZ74LV273

Plastic DIP

SOIC

chip

T_A= -40° to 125° C for all packages

PIN ASSIGNMENT

RESET

LOGIC DIAGRAM

18 D7

17 D6

16 Q6

15 Q5

14 D5

13 D4

12 Q4

11 CLOCK

GND

FUNCTION TABLE

Inputs

Clock

Output

Reset

no change

PIN 20=V_CC

PIN 10 = GND

H= high level

L = low level

X = don’t care

Z = high impedance

INTEGRAL

12 3 4 5 6 7

中文翻译

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