Datasheet > IZ74LV174

IZ74LV174

更新时间： 2024-09-14 22:08:03

品牌	Logo	应用领域
INTEGRAL		触发器
页数	文件大小	规格书
6页	54K
描述
Hex D-type flip-flop with reset; positive edge-trigger

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数据手册

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IZ74LV174 数据手册

TECHNICAL DATA

IN74LV174

Hex D-type flip-flop with reset; positive edge-trigger

The 74LV174 is a low–voltage Si–gate CMOS device and is pin and

function compatible with the 74HC/HCT174.

The 74LV174 has six edge–triggered D–type flip–flops with individual D

inputs and Q outputs. The common clock (CP) and master reset (MR)

inputs load and reset (clear) all flip–flops simultaneously.

The register is fully edge–triggered. The state of each D input, one set–

up time prior to the LOW–to–HIGH clock transition, is transferred to the

corresponding output of the flip–flop.

A LOW level on the MR input forces all outputs LOW, independently of

clock or data inputs.

The device is useful for applications requiring true outputs only and

clock and master reset inputs that are common to all storage elements.

ORDERING INFORMATION

Output voltage levels are compatible with input levels of CMOS,

NMOS and TTL IC_S

IN74LV174N Plastic

IN74LV174D SOIC

IZ74LV174 Chip

Supply voltage range: 1.2 to 5.5 V

Low input current: 1.0 mÀ; 0.1 mÀ at Ò = 25 °Ñ

Output current: 6 mA at Vcc = 3.0 V; 12 mA at Vcc = 4.5 V

High Noise Immunity Characteristic of CMOS Devices

T_A= -40° to 125° C for all packages

PIN ASSIGNMENT

15 Q5

14 D5

13 D4

12 Q4

LOGIC DIAGRAM

10 Q3

GND

FUNCTION TABLE

Inputs

Outputs

PIN 16=V_CC

PIN 08 = GND

no change

H= high level

L = low level

X = don’t care

INTEGRAL

12 3 4 5 6

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