Data Sheet
JUNE 2000
Revision 0.2
IXF6401
Broadband Access Processor
General Description
Features
Flexibility, scalability, effficiency & integration of
different traffic types for a single network is the beauty of
the IXF6401 Broadband Access Processor. Enabling ease
of OEM development, the IXF6401 provides industry
standard interfaces for 64-bit/66 Mhz PCI Bus, 64-bit
SSRAM/SDRAM Local Memory (LM) Bus and UTOPIA
levels 1, 2 ATM & POS interfaces for direct coupling of a
broad range of Layer 1 physical interfaces.
• State of the Art Process Technology
• Sophisticated Buffer Management
• Comprehensive Support
• LANE Hardware Assist
• Wide Range of Applications
• PCI 2.1 Compliance
The IXF6401’s 64-bit, 66Mhz LM Bus acts in concert with
the 64-bit, 66 Mhz PCI Bus to provide up to 8 Gbps of bus
bandwidth. An on-board DMA “engine” controls access to
and from both the PCI Bus and the LM Bus and runs in
master or slave modes.
• Highest Performance
• Extensive VC Traffic Shaping & Policing
• Upper Layer Assist
• ATM & POS UTOPIA Support
The feature rich IXF6401 obtains its full speed by using
extensive & dedicated hardware-based state machines.
OEMs can use APIs that run on top of the 6401’s device
driver to achieve any value added differentiated service.
IXF6401
Block Diagram
Reassembly
or
Rx-UTOPIA
POS Interface
Rx-DMA
Rx- FIFO1
2KB
PCI
Master
64 bit
Receive DMA,
Receive Report
Generator
CMD Queue
Rx-packet
Enqueue Engine
8, 16 or 32 bit
66 MHz
Rx-DMA
CMD Queue
PCI
Slave
Rx
Tx
Traffic
Shaper
Tx
Time
Wheel
Scheduler
Tx
Tx
Packet
Pointer
PCI 2 LM
LM 2 PCI
CPU DMA
Buffer Pools
Manager
Packet
Enqueue
Engine
LM
Slave
Segmentation
or
Packet Dequeue
Engine
Tx-UTOPIA
Tx- CRC 32
Generator
Tx-DMA
Tx- FIFO1
1KB
LM
Master
64 bit
66 MHz
SSRAM
SDRAM
Interface
Transmit DMA,
Transmit Report
Generator
POS Interface
8, 16 or 32 bit
CMD Queue
Tx-DMA
CMD Queue
CD00016